Configurable Enhanced Modular IO Subsystem (eMIOS200)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
657
FEN
FLAG Enable
The FEN bit allows the unified channel FLAG bit to generate an interrupt signal or a DMA request
signal (the type of signal to be generated is defined by the DMA bit).
0 Disable (FLAG does not generate an interrupt or DMA request)
1 Enable (FLAG generates an interrupt or DMA request)
FORCMA
Force Match A
For output modes, the FORCMA bit is equivalent to a successful comparison on comparator A
(except that the FLAG bit is not set). This bit is cleared by reset and is always read as 0. This bit is
valid for every output operation mode which uses comparator A, otherwise it has no effect.
0 Has no effect
1 Force a match at comparator A
Note:
For input modes, the FORCMA bit is not used and writing to it has no effect.
FORCMB
Force Match B
For output modes, the FORCMB bit is equivalent to a successful comparison on comparator B
(except that the FLAG bit is not set). This bit is cleared by reset and is always read as 0. This bit is
valid for every output operation mode which uses comparator B, otherwise it has no effect.
0 Has no effect.
1 Force a match at comparator B.
Note:
For input modes, the FORCMB bit is not used and writing to it has no effect.
BSL
Bus Select
The BSL bits are used to select either one of the counter buses or the internal counter to be used
by the unified channel.
Table 22-8. EMIOS_CCR field description (continued)
Field
Description
BSL
Selected bus
00
All channels: Counter bus[A].
Note:
When BSL = 0, Channel 23 must be in MCB mode.
01
• Counter bus[B] is driven by Channel 0 and can supply
time base to channels 0 to 7.
• Counter bus[C] is driven by Channel 8 and can supply
time base to channels 8 to 15.
• Counter bus[D] is driven by channel 16 and can supply
time base to channels 16 to 23.
Note:
When BSL = 1, Channels 0, 8 and 16 must be in MCB
mode.
10
Reserved
11
All channels: internal counter
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