NXP Semiconductors MPC5644A, Reference Manual, Page: 1454 / 1735

FlexRay Communication Controller (FlexRay)
MPC5644A Microcontroller Reference Manual, Rev. 6
1454 Freescale Semiconductor
33.5.2 Register descriptions
This section provides detailed descriptions of all registers in ascending address order, presented as 16-bit
wide entities
Table 33-4 provides a key for the register figures and register tables.
Message Buffers Configuration, Control, Status
0x0100 Message Buffer Configuration, Control, Status Register 0 (FR_MBCCSR0) R/W on page
33-1527
0x0102 Message Buffer Cycle Counter Filter Register 0 (FR_MBCCFR0) R/W on page
33-1529
0x0104 Message Buffer Frame ID Register 0 (FR_MBFIDR0) R/W on page
33-1530
0x0106 Message Buffer Index Register 0 (FR_MBIDXR0) R/W on page
33-1531
... ... ... ...
0x04F8 Message Buffer Configuration, Control, Status Register 127 (FR_MBCCSR127) R/W on page
33-1527
0x04FA Message Buffer Cycle Counter Filter Register 127 (FR_MBCCFR127) R/W on page
33-1529
0x04FC Message Buffer Frame ID Register 127 (FR_MBFIDR127) R/W on page
33-1530
0x04FE Message Buffer Index Register 127 (FR_MBIDXR127) R/W on page
33-1531
Table 33-4. Register access conventions
Convention Description
Depending on its placement in the read or write row, indicates that the bit is not readable or not
writeable
R* Reserved bit or field; will not be changed—Application must not write any value different from the
reset value
FIELDNAME Identifies the field—Its presence in the read or write row indicates that it can be read or written.
Register field types
rwm A read/write bit that may be modified by a hardware in some fashion other than by a reset
w1c Write one to clear—A flag bit that can be read, is cleared by writing a one; writing 0 has no effect
Reset value
0 Resets to zero
Table 33-3. FlexRay memory map (continued)
Offset Register Access Location