NXP Semiconductors MPC5644A, Reference Manual, Page: 1607 / 1735

FlexRay Communication Controller (FlexRay)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1607
33.6.21 Lower bit rate support
The CC supports a number of lower bit rates on the FlexRay bus channels. The lower bit rates are
implemented by modifying the duration of the microtick
pdMicrotick , the number of samples per microtick
pSamplesPerMicrotick , the number of samples per bit cSamplesPerBit , and the strobe offset cStrobeOffset.
The application configures the FlexRay channel bit rate by setting the BITRATE field in the Module
Configuration Register (FR_MCR) . The protocol values are set internally. The available bit rates, the
related BITRATE field configuration settings and related protocol parameter values are shown in
Table 33-127 .
NOTE
The bit rate of 8 Mbit/s is not defined by the FlexRay Communications
System Protocol Specification, Version 2.1 Rev A.
33.6.22 PE data memory (PE DRAM)
The PE Data Memory (PE DRAM) is 128 word, 16-bit wide memory with byte access, which contains the
program data of the PE internal CPU. The PE DRAM is divided into two banks, 8-bit each. The memory
data [7:0] are assigned to BANK0, the memory data [15:8] are assigned to BANK1.
The FlexRay module provides means to access the PE DRAM from the application. The PE DRAM
application access is initiated and controlled via
PE DRAM Access Register (FR_PEDRAR) and PE
DRAM Data Register (FR_PEDRDR) . This functionality is used to check the memory error detection.
Table 33-127. FlexRay channel bit rate control
FlexRay channel
bit rate
[Mbit/s]
FR_MCR.BITRATE
pd
Mic
roti
c
k
[ns]
g
d
S
a
m
pleClo
ckPer
io
d
[ns]
p
S
amples
PerMicro
tick
cSa
m
ples
Pe
rBit
c
S
tro
b
eOf
fse
t
10.0 000 25.0 12.5 2 8 5
8.0 011 25.0 12.5 2 10 6
5.0 001 25.0 25.0 1 8 5
2.5 010 50.0 50.0 1 8 5
Table 33-128. PE DRAM layout
ADDR BANK1 BANK0
0x00 byte1 byte0
0x01 byte3 byte2
...
0x7F byte255 byte254