NXP Semiconductors MPC5644A, Reference Manual, Page: 653 / 1735

Configurable Enhanced Modular IO Subsystem (eMIOS200)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 653
22.4.3.1 eMIOS200 Channel A Data Register (EMIOS_CADR[n])
Depending on the mode of operation, internal registers A1 or A2, used for matches and captures, can be
assigned to address EMIOS_CADR[
n ]. A1 and A2 are cleared by reset. Table 22-7 summarizes the
EMIOS_CADR[ n ] write and read accesses for all operation modes. For more information see
Section 22.5.1.1, Channel modes of operation .
22.4.3.2 eMIOS200 Channel B Data Register (EMIOS_CBDR[n])
Depending on the mode of operation, internal registers B1 or B2 can be assigned to address
EMIOS_CBDR[
n ]. Both B1 and B2 are cleared by reset. Table 22-7 summarizes the EMIOS_CBDR write
and read accesses for all operation modes. For more information see Section 22.5.1.1, Channel modes of
operation .
Depending on the channel’s configuration, it may or may not have the EMIOS_CBDR. This means that if
at least one mode that requires the register is implemented, then the register is present. Otherwise, it is
absent. MPC5644A has register B (EMIOS_CBDR) in all channels.
Offset: UC[ n ] base a 0x0000 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0
A[0:23]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
A[0:23]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 22-6. eMIOS200 Channel A Data Register (EMIOS_CADR[n])
Offset: UC[ n ] base a 0x0004 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 B[0:23]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R B[0:23]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 22-7. eMIOS200 Channel B Data Register (EMIOS_CBDR[n])
Table 22-7. EMIOS_CADR[n], EMIOS_CBDR[n], and EMIOS_ALTA[n] values assignment
Operation mode
Register access
write read write read alt write alt read
GPIO A1, A2 A1 B1,B2 B1 A2 A2