NXP Semiconductors MPC5644A, Reference Manual, Page: 1049 / 1735

Enhanced Queued Analog-to-Digital Converter (EQADC)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1049
S
25.5.2.16
EQADC
CFIFO Registers (EQADC_CFxRw) (x=0, ..,5; w=0, .., 3)
The EQADC CFIFO Registers (EQADC_CFxRw) (x=0, .., 5; w=0, .., 3) provide visibility of the contents
of a CFIFO for debugging purposes. Each CFIFO has four registers which are uniquely mapped to its four
32-bit entries. Refer to
Section 25.6.4, EQADC Command FIFOs , for more information on CFIFOs. These
registers are read only. Data written to these registers is ignored.
Table 25-27. STAC Bus Timebase Bits Selection
REDBSm[0:3] Selected Bits
0b0000 TBASE m [0:15]
0b0001 TBASE m [1:16]
0b0010 TBASE m [2:17]
0b0011 TBASE m [3:18]
0b0100 TBASE m [4:19]
0b0101 TBASE m [5:20]
0b0110 TBASE m [6:21]
0b0111 TBASE m [7:22]
0b1000 TBASE m [8:23]
Others Reserved
Table 25-28. SRVm valid values
SRVm[0:3] Time Base
0b0000 eTPU engine A, TCR1
0b0001 Reserved
0b0010 eTPU engine A, TCR2
0b0011 Reserved
0b0100–0b1111 Reserved