NXP Semiconductors MPC5644A, Reference Manual, Page: 1372 / 1735

Enhanced Serial Communication Interface (ESCI)
MPC5644A Microcontroller Reference Manual, Rev. 6
1372 Freescale Semiconductor
31.4.5.3.12 Wake-up frame reception
This section describes the reception process when the receiver is in the Wake-up state.
When the required number of frame bits have been received, the payload bits of the received frame are
transferred into
SCI data register (eSCI_DR) if the RDRF flag is 0.
If the address-mark wake-up mode is selected and the received frame has the address bit set, the receive
data register full flag RDRF in Interrupt Flag and Status Register 1 (eSCI_IFSR1) is set. If the receive
interrupt enable bit RIE in the Interrupt Flag and Status Register 1 (eSCI_IFSR1) is set, the RDRF interrupt
request is generated. The RWU bit is cleared, and the receiver enters the Run state via the wake1 transition.
If the idle line wake-up mode is selected and the receiver has detected an idle character, The RWU bit is
cleared, and the receiver enters the Ready state via the wake0 transition.
If any of the receiver errors described in Section 31.4.5.4, Reception error reporting ” have been occurred,
that corresponding flags will be set.
31.4.5.3.13 Bit sampling
The receiver samples the selected receiver input (see Section 31.4.5.3.2, Receiver input mode selection ”)
with the receiver clock RCLK. The bit sampling for start bit detection is shown in Figure 31-32 , the bit
sampling for data and stop bit reception is shown in Figure 31-33 . The samples indicated by dashed arrows
are not used by the receiver. The received data bits are transferred into the internal shift register after the
data strobing. If noise or framing errors were detected, this is flagged as described in
Section 31.4.5.4,
Reception error reporting ”
31.4.5.3.14 Bit synchronization
To adjust for baud rate mismatch, a synchronization of the cyclic receive sample counter RSC is performed
during start bit reception as described in
Section 31.4.5.3.15, Start Bit Sampling ”.
31.4.5.3.15 Start Bit Sampling
Figure 31-32. Start Bit Sampling and Strobing
The sampling of the start bit consists of three phases, the start bit qualification, the start bit verification,
and the start bit noise detection.
Sampled Value
RCLK
START BIT
Receiver Input
START BIT
QUALIFICATION
1 1 1 1 1 0 0 0 0 0 0 0
6 7 8 9 10 1 2
sample counter reset
3
RSC
4 5 6 7
0
8 9 10 11 12 13 14 15 16 1
0 0
START BIT
VERIFICATION
START BIT NOISE
DETECTION
data strobing
0 1 0 0 1 0 0 0
2
sample counter wrap