NXP Semiconductors MPC5644A, Reference Manual, Page: 290 / 1735

External Bus Interface (EBI)
MPC5644A Microcontroller Reference Manual, Rev. 6
290 Freescale Semiconductor
14.4.1.4 EBI Base Registers (EBI_BR0-EBI_BR3, EBI_CAL_BR0-3)
The EBI Base Registers are used to define the base address and other attributes for the corresponding chip
select.
Figure 14-5. EBI Base Registers (EBI_BR0-EBI_BR3, EBI_CAL_BR0-3)
E0x10, E0x18, E0x20, E0x28,
E0x40, E0x48, E0x50, E0x58
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R BA
W
RESET:
1
1
Some upper bits of the BA field may be tied to a fixed value, in which case the reset value is this fixed value
and not zero. Refer to
Section 14.1, Information Specific to This Device , to see which bits this applies to, if any.
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
BA
0 0 0 PS 0 0 0
AD_M
UX
BL
WEBS TBDI
P
0
SET
A
BI
V
W
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
= Unimplemented or Reserved
Table 14-8. EBI Base Registers (EBI_BR0-EBI_BR3, EBI_CAL_BR0-3) Field Descriptions
Name Description
0-16
BA
BA — Base Address
These bits are compared to the corresponding unmasked address signals among ADDR[0:16] of
the internal address bus to determine if a memory bank controlled by the memory controller is being
accessed by an internal bus master.
Note: An MCU may have some of the upper bits of the BA field tied to a fixed value internally in
order to restrict the address range of the EBI for that MCU. Refer to the device-specific
documentation to see which bits are tied off, if any, for a particular MCU. Tied-off bits can be
read but not written. These bits are ignored by the EBI during the chip-select address
comparison. However, the internal bridge of the MCU most likely requires that the chip-select
banks be located in memory regions corresponding to the fixed values chosen.
20
PS
PS — The PS bit determines the data bus width of transactions to this chip-select bank.
Note: In the case where the DBM bit in EBI_MCR is set for 16-bit Data Bus Mode, the PS bit value
is ignored and is always treated as a ’1’ (16-bit port).
1: 16-bit port
0: 32-bit port
24
AD_MUX
AD_MUX — Address on Data Bus Multiplexing
The AD_MUX bit controls whether accesses for this chip select have the address driven on the data
bus in the address phase of a cycle
1: Address on Data Multiplexing Mode is enabled for this chip select.
0: Address on Data Multiplexing Mode is disabled for this chip select.