NXP Semiconductors MPC5644A, Reference Manual, Page: 991 / 1735

Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 991
• T2: hold execution for SPRAM access, from clock pulse T2 until one of the next T2 clock pulses
of another microcycle.
• T4: hold execution in debug mode or stall, from clock pulse T4 until one of the next T4 clock pulses
of another microcycle.
Figure 24-77 and Figure 24-78 shows the timing of T2 and T4 timing states, respectively.
Figure 24-77. T2 timing
Figure 24-78. T4 timing
24.7.1.2 Input/Output signal delays
The synchronizer, filter and edge detection logic delay the input signal transitions.
T4 T2 T2 T2 T2
T2 1st 2nd T2
T4 T2 T4 T2 T CLOCKS
SYS.CLOCK
Nth T2
WAIT-T2
T4

PC
A1 A2
T4
T4
A2 A3
T2
(A1) (A0) (A1)

INST
T2 T4 T4 T4 T4
T4 1st 2nd T4
T2 T4 T2 T4 T CLOCKS
SYS.CLOCK
Nth T4
WAIT-T4
T2

PC A1
A2
T2
T2
A2
T4
A3
T4
(A1) (A1) (A2)

INST