NXP Semiconductors MPC5644A, Reference Manual, Page: 1304 / 1735

Deserial Serial Peripheral Interface (DSPI)
MPC5644A Microcontroller Reference Manual, Rev. 6
1304 Freescale Semiconductor
Figure 30-37. Peripheral chip select strobe timing
The delay between the assertion of the PCS signals and the assertion of PCSS is selected by field
DSPI_CTAR[PCSSCK] based on the following formula:
Eqn. 30-5
At the end of the transfer the delay between PCSS negation and PCS negation is selected by field
DSPI_CTAR[PASC] based on the following formula:
Eqn. 30-6
Table 30-37 shows an example of how to compute the t
pcssck
delay.
Table 30-38 shows an example of how to compute the t
pasc
delay.
The PCSS signal is not supported when Continuous Serial Communication SCK or TSB mode are enabled.
30.9.6 Transfer formats
The SPI serial communication is controlled by the Serial Communications Clock (SCK) signal and the
PCS signals. The SCK signal provided by the master device synchronizes shifting and sampling of the data
on the SIN and SOUT pins. The PCS signals serve as enable signals for the slave devices.
When the DSPI is the bus master, the CPOL and CPHA bits in the DSPI Clock and Transfer Attributes
Registers (DSPI_CTARx) select the polarity and phase of the serial clock, SCK. The polarity bit selects
the idle state of the SCK. The clock phase bit selects if the data on SOUT is valid before or on the first
SCK edge.
When the DSPI is the bus slave, CPOL and CPHA bits in the DSPI_CTAR0 (SPI) or DSPI_CTAR1 (DSI)
select the polarity and phase of the serial clock. Even though the bus slave does not control the SCK signal,
Table 30-37. Peripheral chip select strobe assert computation example
f
sys
PCSSCK Prescaler Delay before transfer
100 MHz 0b11 7 70.0 ns
Table 30-38. Peripheral chip select strobe negate computation example
f
sys
PASC Prescaler Delay after transfer
100 MHz 0b11 7 70.0 ns
t
PCSSCK
PCSS
PCSx
t
PASC
t
PCSSCK
1
f
SYS
---------- PCSSCK

=
t
PASC
1
f
SYS
---------- PASC

=