NXP Semiconductors MPC5644A, Reference Manual, Page: 295 / 1735

External Bus Interface (EBI)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 295
14.5 Functional Description
14.5.1 External Bus Interface Features
14.5.1.1 32-Bit Data Bus (16-bit Data Bus Mode also supported)
The entire 32-bit data bus is available for external memory accesses. There is also a 16-bit Data Bus Mode
available via the DBM bit in EBI_MCR. See
Section 14.2.3.5, 16-Bit data bus mode .
14.5.1.2 Multiplexed Address on Data Pins (single master)
When this mode is enabled, the address shows up on the data pins during the address phase of the cycle.
This mode can be enabled separately for non-chip-select accesses and per chip-select access. See
Section 14.2.3.6, Multiplexed address on data bus mode .
14.5.1.3 Memory Controller with Support for Various Memory Types
The EBI contains a memory controller that supports a variety of memory types, including synchronous
burst mode flash and SRAM, and asynchronous/legacy flash and SRAM with a compatible interface.
Each CS bank is configured via its own pair of Base and Option Registers. Each time an internal to external
bus cycle access is requested, the internal address is compared with the base address of each valid Base
Register (with 17 bits having mask). See
Figure 14-7 . If a match is found, the attributes defined for this
bank in its BR and OR are used to control the memory access. If a match is found in more than one bank,
the lowest bank matched handles the memory access (e.g., bank 0 is selected over bank 1).
A match on a valid calibration chip-select register overrides a match on any non-calibration chip-select
register, with CAL_CS0 having the highest priority. Thus the full priority of the chip-selects is:
CAL_CS0,...,CAL_CS3,CS0,...,CS3.