NXP Semiconductors MPC5644A, Reference Manual, Page: 279 / 1735

External Bus Interface (EBI)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 279
14.2.3.2 Module disable mode
The Module Disable Mode is used for MCU power management. The clock to the non-memory mapped
logic in the EBI can be stopped while in Module Disable Mode. Internal master requests made to the
external bus in Module Disable Mode are terminated with transfer error. Module Disable Mode is entered
when MDIS=1 in the EBI_MCR.
14.2.3.3 Stop mode
When a request is made to enter Stop Mode (controlled in device logic outside EBI), the EBI block
completes any pending bus transactions and acknowledges the stop request. After the acknowledgement,
the system clock input may be shut off by the clock driver on the MCU. While the clocks are shut off, the
EBI is not accessible. While in stop mode, accesses to the EBI from the internal master will terminate with
transfer error.
14.2.3.4 Slower-speed modes
In slower-speed modes, the external CLKOUT frequency is divided (by 2, 3, etc.) compared with that of
the internal system bus. The EBI behavior remains dictated by the mode of the EBI, except that it drives
and samples signals at the CLKOUT frequency rather than the internal system frequency. This mode is
selected by writing a clock control register in a block outside of the EBI. Refer to the device-specific
documentation to see which slower-speed modes are available for a particular MCU (1/2, 1/3, etc.).
14.2.3.5 16-Bit data bus mode
For MCUs that have only 16 data bus signals pinned out, or for systems where the use of a different
multiplexed function (e.g. GPIO) is desired on 16 of the 32 data pins, the EBI supports a 16-bit Data Bus
Mode. In this mode, only 16 data signals are used by the EBI. The user can select which 16 data signals
are used (DATA[0:15] or DATA[16:31]) by writing the D16_31 bit in the EBI_MCR.
For EBI-mastered accesses, the operation in 16-bit Data Bus Mode (DBM=1, PS=x) is similar to a
chip-select access to a 16-bit port in 32-bit Data Bus Mode (DBM=0, PS=1), except for the case of a
non-chip-select access of exactly 32-bit size.
EBI-mastered non-chip-select accesses of exactly 32-bit size are supported via a two (16-bit) beat burst
for both reads and writes. See
Section 14.5.2.9, Non-chip-select burst in 16-bit data bus mode .
Non-chip-select transfers of non-32-bit size are supported in standard non-burst fashion.
16-bit Data Bus Mode is entered when DBM=1 in the EBI_MCR. Some MCUs may have DBM=1 by
default out of reset. See the device-specific documentation for the DBM and D16_31 reset values.
14.2.3.6 Multiplexed address on data bus mode
This mode covers several cases aimed at reducing pin count on MCU and external components. In this
mode, the DATA pins will drive (for internal master cycles) the address value on the first clock of the cycle
(while TS is asserted).The memory controller supports per-chip-select selection of multiplexing
address/data through the BRx[AD_MUX] bit.