NXP Semiconductors MPC5644A, Reference Manual, Page: 1123 / 1735

Enhanced Queued Analog-to-Digital Converter (EQADC)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1123
NOTE
Due to legacy reasons, the EQADC will always wait 120 ADC clocks before
issuing the first conversion command following the enabling of one of
on-chip ADCs, or the exiting of stop mode. There are two independent
counters checking for this delay: one clocked by ADC0_CLK and another
by ADC1_CLK. Conversion commands can start to be executed whenever
one of these counters completes counting 120 ADC clocks.
25.6.6.2 ADC Clock and Conversion Speed
The clock input to the ADCs is defined by setting the ADC0/1_ODD_PS, the ADC0/1_CLK_SEL and the
ADC0/1_CLK_PS fields in the
Section 25.5.3.1, ADC0/1 Control Registers (ADC0_CR and ADC1_CR) .
When the ADC0/1_CLK_SEL is set, the ADC clock frequency is the same as the system clock, but it has
the inverted phase. When it is clear, the ADC0/1_ODD_PS and the ADC0/1_CLK_PS fields select the
clock divide factor by which the system clock will be divided as showed in
Table 25-35 . The ADC clock
frequency is calculated as below and it must not exceed 15 MHz. This is also the maximum frequency of
system clock when the ADC0/1_CLK_SEL is asserted.
Figure 25-76 depicts how the ADC clocks for ADC0 and ADC1 are generated.
Figure 25-76. ADC0/1 Clock Generation
ADCClockFrequency
SystemClockFrequency MHz
 
SystemClockDivideFactor
---------------------------------------------------------------------------------- ADCClockFrequency 15MHz
  
; =
Divide by:
2, 3, 4, .. , 63, 64, 65
ADC0 Control Register
ADC0_CLK_PS
To ADC0
System Clock Divider
System Clock
ADC0Clock
SEL
ADC0_CLK_SEL
Divide by:
2, 3, 4, .. , 63, 64, 65
ADC1 Control Register
ADC1_CLK_PS
To ADC1
System Clock Divider
System Clock
ADC1Clock
SEL
ADC1_CLK_SEL
ADC0_ODD_PS
ADC1_ODD_PS