NXP Semiconductors MPC5644A, Reference Manual, Page: 1254 / 1735

Deserial Serial Peripheral Interface (DSPI)
MPC5644A Microcontroller Reference Manual, Rev. 6
1254 Freescale Semiconductor
30.4.1 SPI configuration
The SPI configuration allows the DSPI to send and receive serial data. This configuration allows the DSPI
to operate as a basic SPI block with internal FIFOs supporting external queues operation. Transmit data
and received data reside in separate FIFOs. The host CPU or a DMA controller read the received data from
the receive FIFO and write transmit data to the transmit FIFO.
For queued operations the SPI queues can reside in system RAM, external to the DSPI. Data transfers
between the queues and the DSPI FIFOs are accomplished by a DMA controller or host CPU.
Figure 30-2
shows a system example with DMA, DSPI and external queues in system RAM.
Figure 30-2. DSPI with queues and DMA
30.4.2 DSI configuration
The DSI configuration supports pin count reduction by serializing eTPU and eMIOS output channels or
bits from a memory-mapped register and shifting them out with a SPI-like protocol. The DSPI deserializes
the received data, and provides the received data to the eTPU’s and eMIOS’ input channels, the SIU IRQ
inputs, or to a memory-mapped register in the DSPI. See
Section 30.9.17, DSPI connections to eTPU_A,
eMIOS and SIU ” for the source of the serialization data for each DSPI module.
Figure 30-3 shows an example of how a master DSPI block connects to a DSI slave in DSI configuration.
System RAM
DSPI
DMA Controller
TX Queue
RX FIFO
TX FIFO
Shift Register
Data
Data
Addr/Ctrl
RX Queue
Data
Data
Addr/Ctrl
Done
Req