NXP Semiconductors MPC5644A, Reference Manual, Page: 376 / 1735

Interrupt Controller (INTC)
MPC5644A Microcontroller Reference Manual, Rev. 6
376 Freescale Semiconductor
15.6.5 Priority ceiling protocol
15.6.5.1 Elevating priority
The PRI field in INTC current priority register (INTC_CPR) is elevated in the OSEK PCP to the ceiling
of all of the priorities of the ISRs that share a resource. This protocol therefore allows coherent accesses
of the ISRs to that shared resource.
For example, ISR1 has a priority of 1, ISR2 has a priority of 2, and ISR3 has a priority of 3. They all share
the same resource. Before ISR1 or ISR2 can access that resource, they must raise the PRI value in
INTC_CPR to 3, the ceiling of all of the ISR priorities. After they release the resource, the PRI value in
INTC_CPR can be lowered. If they do not raise their priority, then ISR2 can preempt ISR1, and ISR3 can
preempt ISR1 or ISR2, possibly corrupting the shared resource. Another possible failure mechanism is
deadlock. If the higher priority ISR needs the lower priority ISR to release the resource before it can
continue, but the lower priority ISR cannot release the resource until the higher priority ISR completes and
execution returns to the lower priority ISR.
Using the PCP instead of disabling processor recognition of all interrupts eliminates the time when
accessing a shared resource that all higher priority interrupts are blocked. For example, while ISR3 cannot
preempt ISR1 while it is accessing the shared resource, all of the ISRs with a priority higher than 3 can
preempt ISR1.
15.6.5.2 Ensuring coherency
Non-coherent accesses to a shared resource can occur. As an example, ISR1 and ISR2 both share a
resource. ISR1 has a lower priority, therefore it executes and then writes the new PRI value in the current
priority register (INTC_CPR). The next instruction writes a value to a shared coherent data block.
If INTC asserts the ISR2 interrupt request to the processor just before or at the same time as the first ISR1
write, it is possible for both the ISR1 and ISR2 writes to execute while the processor responds to the INTC
request, discards the transactions, and flushes the processing pipeline. However, ISR2 cannot access the
data block coherently because the data block is now corrupted.
OSEK uses the GetResource and ReleaseResource system services to manage access to a shared resource.
To prevent corrupting a coherent data block, use the following code to modify the PRI in INTC_CPR.
Interrupts must be enabled before executing the following GetResource code sequence:
GetResource:
raise PRI
mbar
isync
ReleaseResource:
mbar
lower PRI