NXP Semiconductors MPC5644A, Reference Manual, Page: 71 / 1735

Signal Properties
MPC5
644A
Micro
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Re
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Man
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Fre
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71
DSPI_B_SOUT
DSPI_C_PCS[5]
GPIO[104] DSPI B data output
DSPI C peripheral chip select
GPIO P
A1
G
01
10
00 104 O
O
I/O
VDDEH6
Medium
— / Up — / Up 113 G13 J19
DSPI_B_PCS[0]
DSPI_D_PCS[2]
GPIO[105] DSPI B peripheral chip select
DSPI D peripheral chip select
GPIO P
A1
G
01
10
00 105 I/O
O
I/O
VDDEH6
Medium
— / Up — / Up 111 G16 J21
DSPI_B_PCS[1]
DSPI_D_PCS[0]
GPIO[106] DSPI B peripheral chip select
DSPI D peripheral chip select
GPIO P
A1
G
01
10
00 106 O
I/O
I/O
VDDEH6
Medium
— / Up — / Up 109 H16 J22
DSPI_B_PCS[2]
DSPI_C_SOUT
GPIO[107] DSPI B peripheral chip select
DSPI C data output
GPIO P
A1
G
01
10
00 107 O
O
I/O
VDDEH6
Medium
— / Up — / Up 107 H15 K22
DSPI_B_PCS[3]
DSPI_C_SIN
GPIO[108] DSPI B peripheral chip select
DSPI C data input
GPIO P
A1
G
01
10
00 108 O
I
I/O
VDDEH6
Medium
— / Up — / Up 114 G14 J20
DSPI_B_PCS[4]
DSPI_C_SCK
GPIO[109] DSPI B peripheral chip select
SPI clock pin for DSPI module
GPIO P
A1
G
01
10
00 109 O
I/O
I/O
VDDEH6
Medium
— / Up — / Up 105 H14 K20
DSPI_B_PCS[5]
DSPI_C_PCS[0]
GPIO[110] DSPI B peripheral chip select
DSPI C peripheral chip select
GPIO P
A1
G
01
10
00 110 O
I/O
I/O
VDDEH6
Medium
— / Up — / Up 104 J13 L19
eQADC
AN0
18
DAN0+
Single Ended Analog Input
Positive Terminal Diff. Input P — — I
I VDDA
Analog
I / — AN[0] / — 172 B5 C6
AN1
18
DAN0-
Single Ended Analog Input
Negative Terminal Diff. Input P — — I
I VDDA
Analog
I / — AN[1] / — 171 A6 C7
AN2
18
DAN1+
Single Ended Analog Input
Positive Terminal Diff. Input P — — I
I VDDA
Analog
I / — AN[2] / — 170 D6 D7
AN3
18
DAN1-
Single Ended Analog Input
Negative Terminal Diff. Input P — — I
I VDDA
Analog
I / — AN[3] / — 169 C7 D8
AN4
18
DAN2+
Single Ended Analog Input
Positive Terminal Diff. Input P — — I
I VDDA
Analog
I / — AN[4] / — 168 B6 B7
Table 1. MPC5644A signal properties (continued)
Name Function
1
P
A
G
2
PCR
PA
Field
3
PCR
4
I/O
Type
Voltage
5
/
Pad Type
6
Status
7
Package pin #
During Reset
After
Reset
176 208 324