NXP Semiconductors MPC5644A, Reference Manual, Page: 1057 / 1735

Enhanced Queued Analog-to-Digital Converter (EQADC)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1057
Figure 25-37.
EQADC
RFIFO5 Registers (
EQADC
_RF5Rw) (w=0, .., 3)
25.5.3 On-Chip ADC Registers
This section describes a list of registers that control on-chip ADC operation. The ADC registers are not
part of the CPU accessible memory map. These registers can only be accessed indirectly through
configuration commands. There are 4 non memory mapped registers per ADC, plus 12 registers shared by
both ADCs. The address, usage, and access privilege of each register is shown in
Table 25-32 . Data written
to or read from reserved areas of the memory map is undefined.
Their assigned addresses are the values used to set the ADC_REG_ADDRESS field of the read/write
configurations commands bound for the on-chip ADCs. These are half-word addresses. Further, the
following restrictions apply when accessing these registers:
• Registers ADC0_CR, ADC0_GCCR, ADC0_OCCR, ADC0_AGR1/2 and ADC0_AOR1/2 can
only be accessed by configuration commands sent to CBuffer0.
• Registers ADC1_CR, ADC1_GCCR, ADC1_OCCR, ADC1_AGR1/2 and ADC1_AOR1/2 can
only be accessed by configuration commands sent to CBuffer1.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R RFIFO5_DATAw
W
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Register address:
EQADC
_BASE+0x440
Register address: EQADC _BASE+0x444
Register address:
EQADC
_BASE+0x448
Register address: EQADC _BASE+0x44C
Table 25-31.
EQADC
RFIFOx Registers (
EQADC
_RFxRw) (w=0, .., 3) field description
Field Description
0-31
RFIFOx_DATAw
[0:15]
RFIFOx Data w (w = 0, .., 3)
Reading RFIFOx_DATAw returns the value stored on the wth entry of RFIFOx. Each RFIFO
is composed of four 16-bit entries, with register 0 being mapped to the one with the smallest
memory mapped address.