NXP Semiconductors MPC5644A, Reference Manual, Page: 257 / 1735

Memory Protection Unit (MPU)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 257
Chapter 13
Memory Protection Unit (MPU)
13.1 Introduction
The memory protection unit (MPU) provides hardware access control for all memory references generated
in a device. Using preprogrammed region descriptors that define memory spaces and their associated
access rights, the MPU concurrently monitors all system bus transactions and evaluates the
appropriateness of each transfer. Memory references with sufficient access control rights are allowed to
complete, but references that are not mapped to any region descriptor or have insufficient rights are
terminated with a protection error response.
The MPU implements a set of program-visible region descriptors that monitor all system bus addresses.
The result is a hardware structure with a two-dimensional connection matrix, where the region descriptors
represent one dimension and the individual system bus addresses and attributes are the second dimension.
13.1.1 Features
The MPU has these major features:
• Support for 16 memory region descriptors, each 128 bits in size
— Specification of start and end addresses provide granularity for region sizes from 32 bytes to
4 GB
— MPU is invalid at reset, thus no access restrictions are enforced
— 2 types of access control definitions: processor core bus master supports the traditional {read,
write, execute} permissions with independent definitions for supervisor and user mode
accesses; the remaining non-core bus masters (eDMA, FlexRay, and EBI
1
) support {read,
write} attributes
— Automatic hardware maintenance of the region descriptor valid bit removes issues associated
with maintaining a coherent image of the descriptor
— Alternate memory view of the access control word for each descriptor provides an efficient
mechanism to dynamically alter the access rights of a descriptor only
— For overlapping region descriptors, priority is given to permission granting over access
denying as this approach provides more flexibility to system software
• Support for two XBAR slave port connections (SRAM and PBRIDGE)
— For each connected XBAR slave port (SRAM and PBRIDGE), MPU hardware monitors every
port access using the preprogrammed memory region descriptors
— An access protection error is detected if a memory reference does not hit in any memory region
or the reference is flagged as illegal in all memory regions where it does hit. In the event of an
access error, the XBAR reference is terminated with an error response and the MPU inhibits
the bus cycle being sent to the targeted slave device
— 64-bit error registers, one for each XBAR slave port, capture the last faulting address,
attributes, and detail information
1. EBI not available on all packages and is not available, as a master, for customer.