NXP Semiconductors MPC5644A, Reference Manual, Page: 1276 / 1735

Deserial Serial Peripheral Interface (DSPI)
MPC5644A Microcontroller Reference Manual, Rev. 6
1276 Freescale Semiconductor
30.8.2.8 DSPI POP RX FIFO Register (DSPI_POPR)
The DSPI_POPR provides the means to read the RX FIFO. See Section 30.9.2.5, Receive first-in first-out
(RX FIFO) buffering mechanism ” for a description of the RX FIFO operations. Eight or 16-bit read
accesses to the DSPI_POPR have the same effect on the RX FIFO as 32-bit read access.
Address: DSP 0x34
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
TXDATA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
TXDATA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 30-13. DSPI PUSH TX FIFO Register (DSPI_PUSHR) in slave mode
Table 30-15. DSPI_PUSHR field description in slave mode
Field Descriptions
0–31
TXDATA[0:31]
Transmit Data
The TXDATA field holds SPI data to be transferred.
Address: DSP 0x38
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R RXDATA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R RXDATA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 30-14. DSPI POP RX FIFO Register (DSPI_POPR)