NXP Semiconductors MPC5644A, Reference Manual, Page: 530 / 1735

System Integration Unit (SIU)
MPC5644A Microcontroller Reference Manual, Rev. 6
530 Freescale Semiconductor
16.6.21 IMUX Select Register 3 (SIU_ISEL3)
The SIU_ISEL 3 register selects the source for the external eQADC trigger inputs.
Figure 16-206. IMUX Select Register 3 (SIU_ISEL3)
For options 0b01000, 0b01001, 0b10100, 0b10101 for each queue, two trigger sources are logically
ANDed together. The intention is that the PIT provides the regular cyclic trigger, while the eTPU or
eMIOS channels are used to ‘gate’ that cyclic trigger. This way, the ADC can be commanded to make
regular samples but only during a given time or angle window.
28:29
SCKSELD
DSPI_D Clock Input Select. The source of the clock input of DSPI_D when in slave mode is specified
by SCKSELD as follows:
00 DSPI_D_SCK pin
01 Reserved
10 DSPI_B_SCK (Master)
11 DSPI_C_SCK (Master)
30:31
TRIGSELD
DSPI_D Trigger Input Select. The source of the trigger input of DSPI_D for master or slave mode is
specified by TRIGSELD as follows:
00 Reserved
01 Reserved
10 DSPI_B_PCS[4]
11 DSPI_C_PCS[4]
S0x90C
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
0 0 eTSEL5 eTSEL4 eTSEL3
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
eTSEL
3
eTSEL2 eTSEL1 eTSEL0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Table 16-206. eQADC queue0 enhanced trigger selection
eTSEL0 eQADC enhanced trigger input
0 0 0 0 0 GPIO206 (eTRIG0)
0 0 0 0 1 RTI Trigger
0 0 0 1 0 PIT0 Trigger
0 0 0 1 1 PIT1 Trigger
0 0 1 0 0 PIT2 Trigger
Table 16-205. SIU_DISR field description (continued)
Field Description