NXP Semiconductors MPC5644A, Reference Manual, Page: 1527 / 1735

FlexRay Communication Controller (FlexRay)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1527
This register defines the data distortion pattern for the error injection write. The number of valid bits
depends on the selected memory and memory bank as shown in
Table 33-84 .
33.5.2.77 ECC Error Injection Code Register (FR_EEICR)
This register defines the ECC code distortion pattern for the error injection write.
33.5.2.78 Message Buffer Configuration, Control, Status Registers
(FR_MBCCSRn)
The content of these registers comprises message buffer configuration data, message buffer control data,
message buffer status information, and message buffer interrupt flags. A detailed description of all flags
can be found in
Section 33.6.6, Individual message buffer functional description ”
Table 33-87. FR_EEIDR field description
Field Description
DATA Data — The content of this field depends on the error injection mode selected by FR_EERICR[EIM].
EIM = 0: This field defines the XOR distortion pattern for the data written into the memory.
EIM = 1: This field defines the data to be written into the memory.
Base + 0x00FE Write: IDL
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0
CODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 33-108. ECC Error Injection Code Register (FR_EEICR)
Table 33-88. FR_EEICR field description
Field Description
CODE Code — The content of this field depends on the error injection mode selected by FR_EERICR[EIM].
EIM = 0: This field defines the XOR distortion pattern for the ECC checkbits written into the memory.
EIM = 1: This field defines the ECC checkbits written into the memory.
Base + 0x0100 (FR_MBCCSR0)
Base + 0x0108 (FR_MBCCSR1)
...
Base + 0x04F8 (FR_MBCCSR127) Write: MCM, MBT, MTD: POC:config or
MB_DIS
CMT: MB_LCK or MB_DIS
EDT, LCKT, MBIE, MBIF: Normal Mode
Additional Reset: CMT, DUP, DVAL, MBIF: Message Buffer
Disable
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
0
MC
M
MBT MTD
CMT
0 0
MBIE
0 0 0
DU
P
DV
AL
ED
S
LCKS
MB
IF
W
rwm
EDT
LCKT
w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 33-109. Message Buffer Configuration, Control, Status Registers (FR_MBCCSRn)