NXP Semiconductors MPC5644A, Reference Manual, Page: 707 / 1735

Reaction Module (REACM)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 707
6
TAER
Timer Allocation Error
The Timer Allocation Error bit indicates that the channel tried to allocate a timer counter in the
Shared Timer Bank without success. This situation is an indication that the Timer resources
available in the module are not sufficient to execute the required functionality. This error
indication is used during software development and should not occur during normal use of the
module since it may result in incorrect operation. This Flag is set only of the channel is in the
active state.
1 Error occurred during timer allocation
0 No error occurred during timer allocation.
7
SQER
Modulation Word Sequence Error Flag
The SQER bit indicates a Modulation Sequence error occurred, meaning that the time window
which defines a modulation cycle ended in a premature modulation phase. The correct
modulation phase for the time window to close is when SM field in the Modulation Word indicates
no advance , or SM = 00. This Flag is set only of the channel is in the active state.
1 Modulation Sequence Error occurred
0 Modulation Sequence Error did not occur.
8
RAER
Resource Allocation Error Flag
The RAER bit indicates that a resource allocation error occurred. The possible allocation errors
are: Modulation Control Word address is out of available range (including if the
MODULATION_POINTER increments to an inexistent MCW address or wraps to 0x0),
Threshold Value Bank address is out of available range, Hold-off Timer Bank address is out of
available range, Shared Timer Bank address is out of available range, Channel Input Router
points to an inexistent eTPU channel, and when the Hold-off timer is select for both modulation
and sequence advance at the same time (i.e, SM = 10 and MM = 01). Note that the amount of
hardware resources is configuration dependent thus may vary according to module
instantiations in the SoC. This flag is intended to help on the debug of the Reaction Module
during software development and can be set only if the channel is in the
enabled state.
1 Allocation error occurred
0 No allocation error occurred
Note: The condition that sets the RAER bit must be resolved prior to clear the bit, otherwise the
bit can be set again.
9–11
CHOUT[2:0]
Channel Output Monitoring bits
The CHOUT[2:0] Channel Output Monitoring bits provides for the software the ability to monitor
the output provided by the channel. This data is not buffered thus represents the channel output
at the time the CPU read access is done. CHOUT[0] corresponds to the chn_a output,
CHOUT[1] corresponds to the chn_b output and CHOUT[2] corresponds to the ch
n _c output pin.
These bits are available independent of the channel mode or state.
12–18 Reserved, should be cleared.
19
MAXLC
ADC Maximum Limit Flag Clear
The MAXLC clears the MAXL flag if write 0x1. This bit reads always as 0x0. If a set event occurs
at the same time a flag clear is done, the set event has precedence over the clear thus the flag
remains set.
1 Clears MAXL bit
0 No action
20
OCDFC
Open Circuit Detection Flag Clear
The OCDFC clears the OCDF flag if write 0x1. This bit reads always as 0x0
1 Clears OCDF bit
0 No action
Table 23-11. REACM_CHSRn field descriptions (continued)
Field Description