NXP Semiconductors MPC5644A, Reference Manual, Page: 876 / 1735

Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
876 Freescale Semiconductor
Using this mode, the channel can replace software window filtering of qualified transitions with the
channel hardware window. The window opening and closing time can be scheduled for any of the two time
bases or a combination of them.
Ordered Mode with Match B Request, Double Transition (m2_o_dt)
In this mode the channel logic implements a window filter for two detected signal transitions. MRLA
assertion captures its related timebase and enables the assertion of both TDLA and TDLB. MRLB
assertion captures its related timebase and disables the assertion of both TDLA and TDLB. Transitions can
be detected from the microcycle following MRLA assertion until the microcycle on which MRLB is
asserted. The first signal transition (following MRLA assertion) asserts TDLA, captures its related
timebase and enables assertion of TDLB. The second signal transition detection asserts TDLB, blocks
Match B, captures its related timebase and generates the service request.
If both signal transitions occur inside the scheduled window, Match B recognition is blocked. If one or
both signal transitions do not occur inside the scheduled window, Match B recognition generates a match
service request and blocks further transition detections. The microcode can resolve the state using MRLA,
MRLB, TDLA and TDLB, which affect the entry point selection.
Single Match Enhanced Mode (sm_st_e)
This is an enhanced single transition and single match channel mode which provides timing information
of the digital filter delay.
The CaptureA register captures the timebase selected by TBSA due to transition detection specified by
IPACA or match recognition, as in sm_st mode. Initially, the CaptureB register continuously captures the
unfiltered IPACB-selected signal transitions from the digital filter input, directly from the signal
synchronizer. When an IPACA-qualified, filtered transition detection occurs, TDLA is set, MRLA
assertion is blocked, and, in addition, captures into CaptureB are also blocked. On service, CaptureA and
CaptureB (copied into ERTA and ERTB) holds the time of the qualified transition detection (ERTA), and
the time of the last signal transition at the input of the digital filter (ERTB). Subtracting the time in ERTB
from the time in ERTA provides the delay of the digital filter.
In a quiet environment, the two captures provide the accurate delay of the digital filter in granularity of
two system clocks. In a noisy environment, false transitions may be detected at the input of the digital filter
due to the noise, and the delay measurement may be reduced, especially if IPACB selects both edge
detection. The microcode can do sanity checks on this value to recognize noise effects (for example:
calculated delay is less than the minimum delay of the digital filter).
NOTE
In Channel 0, if ETPU_TBCR field AM = 01 (Angle Mode), the unfiltered
input comes from TCRCLK input and the filtered input comes from the
TCRCLK filter output. The edge is selected by IPACA/B, and is
independent of the edge selection by ETPU_TBCR field TCR2CTL.