NXP Semiconductors MPC5644A, Reference Manual, Page: 1314 / 1735

Deserial Serial Peripheral Interface (DSPI)
MPC5644A Microcontroller Reference Manual, Rev. 6
1314 Freescale Semiconductor
NOTE
When in Continuous SCK mode, for the SPI transfer CTAR0 should always
be used, and the TX-FIFO must be clear using the DSPI_MCR[CLR_TXF]
field before initiating transfer.
Figure 30-48. Continuous SCK timing diagram (CONT = 0)
If the CONT bit in the TX FIFO entry is set or the DCONT in the DSPI_DSICR is set, PCS remains
asserted between the transfers. Under certain conditions, SCK can continue with PCS asserted, but with
no data being shifted out of SOUT (SOUT pulled high). This can cause the slave to receive incorrect data.
Those conditions include:
• Continuous SCK with CONT bit set, but no data in the transmit FIFO.
• Continuous SCK with CONT bit set and entering STOPPED state (refer to Section 30.9.1, Start
and stop of DSPI transfers ”).
• Continuous SCK with CONT bit set and entering Stop mode or Module Disable mode.
Figure 30-49 shows timing diagram for Continuous SCK format with Continuous Selection enabled.
Figure 30-49. Continuous SCK timing diagram (CONT = 1)
t
DT
SCK
PCS
SCK
Master SOUT
Master SIN
(CPOL = 0)
(CPOL = 1)
SCK
PCS
SCK
Master SOUT
Master SIN
(CPOL = 0)
(CPOL = 1)
transfer 1 transfer 2