NXP Semiconductors MPC5644A, Reference Manual, Page: 1291 / 1735

Deserial Serial Peripheral Interface (DSPI)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1291
Figure 30-30. SPI and DSI Serial Protocol Overview
Generally more than one slave device can be connected to the DSPI master. Eight Peripheral Chip Select
(PCS) signals of the DSPI masters can be used to select which of the slaves to communicate with.
The three DSPI configurations share transfer protocol and timing properties which are described
independently of the configuration in
Section 30.9.6, Transfer formats ”. The transfer rate and delay
settings are described in Section 30.9.5, DSPI baud rate and clock delay generation .
30.9.1 Start and stop of DSPI transfers
The DSPI has two operating states: STOPPED and RUNNING. The states are independent of DSPI configuration. The default
state of the DSPI is STOPPED. In the STOPPED state no serial transfers are initiated in master mode and no transfers are
responded to in slave mode. The STOPPED state is also a safe state for writing the various configuration registers of the DSPI
without causing undetermined results. In the RUNNING state serial transfers take place.
Bit DSPI_SR[TXRXS] indicates the DSPI’s operating state. The bit is set if the module is in RUNNING state.
The DSPI is started (DSPI transitions to RUNNING) when all of the following conditions are true:
• DSPI_SR[EOQF] bit is clear
• Device is not in the debug mode is or the DSPI_MCR[FRZ] bit is clear
• DSPI_MCR[HALT] bit is clear
The DSPI stops (transitions from RUNNING to STOPPED) after the current frame when any one of the following conditions exist:
• DSPI_SR[EOQF] bit is set
• Device in the debug mode and the DSPI_MCR[FRZ] bit is set
• DSPI_MCR[HALT] bit is set
State transitions from RUNNING to STOPPED occur on the next frame boundary if a transfer is in progress, or immediately if no
transfers are in progress.
30.9.2 Serial peripheral interface (SPI) configuration
The SPI configuration transfers data serially using a shift register and a selection of programmable transfer attributes. The DSPI
is in SPI configuration when field DSPI_MCR[DCONF] is 0b00. The SPI frames can be from 4 to 16 bits long. Host CPU or a
DMA controller transfer the SPI data from the external to DSPI RAM queues to a transmit First-In First-Out (TX FIFO) buffer. The
received data is stored in entries in the Receive FIFO (RX FIFO) buffer. Host CPU or the DMA controller transfer the received
data from the RX FIFO to memory external to the DSPI. The FIFO buffers operation is described in
Section 30.9.2.4, Transmit
first-in first-out (TX FIFO) buffering mechanism , and Section 30.9.2.5, Receive first-in first-out (RX FIFO) buffering mechanism .
The interrupt and DMA request conditions are described in Section 30.9.10, Interrupts/DMA requests .
Shift Register
Baud Rate
Generator
Shift Register
SIN
SIN SOUT
SOUT
SCK
SCK
SS
PCSx
DSPI Master DSPI Slave