NXP Semiconductors MPC5644A, Reference Manual, Page: 1295 / 1735

Deserial Serial Peripheral Interface (DSPI)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1295
• Trigger signal
• Trigger signal combined with a change in data
The four transfer initiation conditions are described in Section 30.9.3.5, DSI transfer initiation control .
Transfer attributes are set during initialization. Field DSPI_DSICR[DSICTAS] determines which of the
DSPI_CTAR registers will control the transfer attributes.
30.9.3.2 Slave mode
In DSI slave mode the DSPI responds to transfers initiated by a SPI or DSI bus master. In this mode the
DSPI does not initiate DSI transfers. Certain transfer attributes such as clock polarity and phase must be
set for successful communication with a DSI master. The DSI slave mode Transfer attributes are set in the
DSPI_CTAR1.
If the CID bit in the DSPI_DSICR is set and the data in the DSPI_COMPR differs from the selected source
of the serialized data, the slave DSPI will assert the MTRIG signal. If the slave’s HT signal is asserted and
the TRRE is set, the slave DSPI asserts MTRIG. These features are included to support chaining of several
DSPI. Details about the MTRIG signal is found in
Section 30.9.3.6, Multiple transfer operation (MTO) .
30.9.3.3 DSI serialization
In the DSI configuration from 4 to 16 bits can be serialized using 2 different sources. The TXSS bit in the
DSPI_DSICR selects between the DSPI DSI Serialization Data Register (DSPI_SDR) and the DSPI DSI
Alternate Serialization Data Register (DSPI_ASDR) as the source of the serialized data. The DSPI_SDR
holds the latest Parallel Input signal values which is sampled at every rising edge of the system clock. The
DSPI_ASDR is written by host software and used as an alternate source of serialized data.
The DSPI_PISR0–3 registers allow to change relative position of the Parallel input pins in the transmitted
frame. Each transmitted frame bit can be selected from 16 adjacent Parallel Inputs by writing IPSn fields.
The IPSn field is treated as a 4-bit integer number, representing numbers from

8 to 7. The Parallel Input
pin number, selected by IPSn field is defined by the difference between sum IPSn field number (n) and the
IPSn field value. If the operation result is negative the number 32 should be added. If the result is higher
than 32, 32 should be subtracted from the result.
For example, IPS0, set to minus 1 (binary 1111), preselects Parallel Input 1 to 0 position in the transmitted
frame.
IPS6, set to 3 (binary 0011), preselects Parallel Input 3 to be bit number 6 in the transmitted frame, while
the value minus 2 (1110) preselects Parallel Input 8.
IPS31, set to minus 8 (binary 1000), preselects Parallel Input 7 to be bit number 31 in the transmitted
frame.
(Of course, the Parallel Input pin state, to be transmitted, should be selected by TXSS and the frame size
should be higher than the bit position in the preselected frame.)
The DSPI_SSR provides additional way to create the frame for transmission. Each bit from this register is
OR’d with the TXSS bit and controls individual transmitted bit source. This way, the transmitted frame
can have any combination of the DSPI_SDR and DSPI_ASDR bits. This feature allows control SPI based