NXP Semiconductors MPC5644A, Reference Manual, Page: 1298 / 1735

Deserial Serial Peripheral Interface (DSPI)
MPC5644A Microcontroller Reference Manual, Rev. 6
1298 Freescale Semiconductor
30.9.3.5.3 Triggered control
For Triggered Control initiation of a transfer is controlled by the Hardware Trigger signal (HT). The TPOL
bit in the DSPI_DSICR selects the active edge of HT. For HT to have any affect, the TRRE bit in the
DSPI_DSICR must be set.
30.9.3.5.4 Triggered or change in data control
For Triggered or Change in Data Control initiation of a transfer is controlled by the HT signal or by the
detection of a change in data to be serialized.
30.9.3.6 Multiple transfer operation (MTO)
In DSI configuration the MTO feature allows for multiple DSPIs within a device to be chained together in
a parallel or serial configuration. The parallel chaining allows multiple DSPIs internal to a device and
multiple SPI devices external to a device to share SCK and PCS signals thereby helping to minimize device
pin count. The serial chaining allows bits from multiple DSPIs to be concatenated into a single DSI frame.
MTO is enabled by setting the MTOE bit in the DSPI_DSICR.
In parallel and serial chaining there is one bus master and multiple bus slaves. The bus master initiates and
controls the transfers, but the DSPI slaves generate trigger signals for the bus DSPI master when an
internal condition in the slave warrants a transfer. The DSPI slaves also propagate triggers from other
slaves to the master. When a DSPI slave detects a trigger signal on its HT input, the slave generates a
trigger signal on the MTRIG output.
Serial and parallel chaining require multiplexing of signals external to the DSPI.
NOTE
TSB operation is not available in MTO mode. TSBC and MTOE bits of
DSPI_DSICR should not be set simultaneously.
30.9.3.6.1 Parallel chaining
Parallel chaining allows the PCS and SCK signals from a Master DSPI to be shared by internal Slave
DSPIs and external Slave SPI devices, thus reducing pin utilization of the MPC5644AMCU. Signal
sharing reduces DSPI pin utilization. An example of a parallel chain is shown in
Figure 30-33 . In this
example, the SOUT and SIN of the three DSPIs connect to separate external SPI devices, which share a
common PCS and SCK.