
Enhanced Direct Memory Access Controller (eDMA)
MPC5644A Microcontroller Reference Manual, Rev. 6
148
Freescale Semiconductor
When minor loop mapping is disabled (EDMA_CR[EMLM] = 0), all 32 bits of TCD
n
word2 are assigned
to the NBYTES field. See
Section 8.3.2.17, Transfer control descriptor (TCD)
for more details.
Offset: EDM 0x0000
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CX
ECX
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
GRP3PRI
GRP2PRI
GRP1PRI
GRP0PRI
EMLM
CLM
HAL
T
HOE
ERGA
ERCA
EDBG
0
W
Reset
1
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
Figure 8-2. eDMA Control Register (EDMA_CR)
Table 8-3. EDMA_CR field descriptions
Field
Description
CX
Cancel Transfer
0 Normal operation
1 Cancel the remaining data transfer. Stop the executing channel and force the minor loop to be
finished. The cancel takes effect after the last write of the current read/write sequence. The CX bit
clears itself after the cancel has been honored. This cancel retires the channel normally as if the
minor loop was completed.
ECX
Error cancel transfer
0 Normal operation
1 Cancel the remaining data transfer in the same fashion as the CX cancel transfer. Stop the
executing channel and force the minor loop to be finished. The cancel takes effect after the last
write of the current read/write sequence. The ECX bit clears itself after the cancel has been
honored. In addition to cancelling the transfer, the ECX treats the cancel as an error condition;
thus updating the EDMA_ESR register and generating an optional error interrupt. See
Section 8.3.2.2, eDMA Error Status Register (EDMA_ESR).
GRP3PRI
Channel group 3 priority
Group 3 priority level when fixed priority group arbitration is enabled.
GRP2PRI
Channel group 2 priority
Group 2 priority level when fixed priority group arbitration is enabled.
GRP1PRI
Channel group 1 priority
Group 1 priority level when fixed priority group arbitration is enabled.
GRP0PRI
Channel group 0 priority
Group 0 priority level when fixed priority group arbitration is enabled.
EMLM
Enable minor loop mapping
0 Minor loop mapping disabled. TCD Word 2 is defined as a 32-bit nbytes field.
1 Minor loop mapping enabled. When set, TCD
n
Word 2 is redefined to include individual enable
fields, an offset field and the NBYTES field. The individual enable fields allow the minor loop offset
to be applied to the source address, the destination address, or both. The NBYTES field is
reduced when either offset is enabled.
Summary of Contents for MPC5644A
Page 2: ...MPC5644A Microcontroller Reference Manual Rev 6 2 Freescale Semiconductor...
Page 24: ...MPC5644A Microcontroller Reference Manual Rev 6 24 Freescale Semiconductor...
Page 26: ...MPC5644A Microcontroller Reference Manual Rev 6 26 Freescale Semiconductor...
Page 52: ...Introduction MPC5644A Microcontroller Reference Manual Rev 6 52 Freescale Semiconductor...
Page 56: ...Memory Map MPC5644A Microcontroller Reference Manual Rev 6 56 Freescale Semiconductor...
Page 1228: ...Decimation Filter MPC5644A Microcontroller Reference Manual Rev 6 1228 Freescale Semiconductor...
Page 1440: ...FlexCAN Module MPC5644A Microcontroller Reference Manual Rev 6 1440 Freescale Semiconductor...