NXP Semiconductors MPC5644A, Reference Manual, Page: 1185 / 1735

Decimation Filter
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1185
Table 26-11. DECFILTER_MSR Register Field Descriptions
Field Description
0
BSY
Decimation Filter Busy indication. The BSY bit indicates that the Decimation Filter is processing
new input data from the master block in normal mode or from the device core in standalone
mode. BSY is not asserted when the filter is disabled (FTYPE = 00). However, the BSY bit is
asserted when the soft reset is executed.
1 Decimation Filter Busy
0 Decimation Filter Idle
1 Reserved, should be cleared.
2–5
DEC_COUNTER
[3:0]
Decimation Counter. The DEC_COUNTER[3:0] field indicates the current value of the
DEC_COUNTER Decimation Counter (see
Figure 26-1 ), which counts the number of input data
samples received by the Decimation Filter. When the value of this counter matches the
DEC_RATE[3:0] Configuration Register field, one decimated result is generated and the
DEC_COUNTER counter is reinitialized at zero. This register is cleared by a soft reset or a flush
command.
6
IDFC
Input Data Flag Clear bit. The IDFC bit clears the IDF Flag bit in the Status Register. This bit is
self negated, therefore it is always read as zero.
1 Clears IDF
0 No action
7
ODFC
Output Data Flag Clear bit. The ODFC bit clears the ODF Flag bit in the Status Register. This bit
is self negated, therefore it is always read as zero.
1 Clears ODF
0 No action
8 Reserved, should be cleared.
9
IBIC
Input Buffer Interrupt Request Clear bit. The IBIC bit clears the IBIF Flag bit in the Status
Register. This bit is self negated, therefore it is always read as zero.
1 Clears IBIF
0 No action
10
OBIC
Output Buffer Interrupt Request Clear bit. The OBIC bit clears the OBIF Flag bit in the Status
Register. This bit is self negated, therefore it is always read as zero.
1 Clears OBIF
0 No action
11 Reserved, should be cleared.
12
DIVRC
DIVR Clear bit. The DIVRC bit clears the DIVR Debug Filter Input Data Read Overrun indication
bit in the Status Register. This bit is self negated, therefore it is always read as zero.
1 Clears DIVR
0 No action
13
OVFC
OVF Clear bit. The OVFC bit clears the OVF Output Overflow bit in the Status Register. This bit
is self negated, therefore it is always read as zero.
1 Clears OVF
0 No action
14
OVRC
OVR Clear bit. The OVRC bit clears the OVR Output Overrun bit in the Status Register. This bit
is self negated, therefore it is always read as zero.
1 Clears OVR
0 No action