NXP Semiconductors MPC5644A, Reference Manual, Page: 1173 / 1735

Decimation Filter
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1173
Figure 26-1. Decimation filter block diagram
26.2.2 Features
The Decimation Filter block includes these distinctive features:
• Selectable 4th order IIR filter, or an 8th order FIR filter
— Input/output with 16-bit (fixed point) two’s complement signed values
— Internal taps with 16-bit (feed-forward portion of first IIR) and 24-bit (feedback portion)
resolutions (fixed point) for two’s complement signed value
— 24-bit programmable filter coefficients (fixed point) for two’s complement signed value
— MAC unit with 51-bit fixed point accumulator
— Convergent rounding methodology
— Two’s complement overflow or saturation selection
— 58 clock cycles to process the input
• Implements a local slave-bus interface to a master block (e.g. the eQADC block)
• Input and output buffers with DMA capability
• Slave-bus interface to device
Control
Coefficient
Register File
Logic
Enable/Clear
Counter
Tx En
MAC Done
Bypass Select
en
data-in 1
data-in 2
Decimated
Result
Intermediary
Result
MAC
done
Coefficient
Select
Clear/Load
Rx Data
PSI
Rx
Decimated
Sample
Tap Data
Filter Tap Result
Bypass Data Path
Data
New
Sample/
Control
Field
PSI
Tx
PSI Slave-Bus Line
Device Slave-Bus Line
En
Data
Decoder
Counter
Filter Tap
Registers
Cascade
Input
Cascade
Output
Integrator
Integration
control signals
External trigger signal