NXP Semiconductors MPC5644A, Reference Manual, Page: 1090 / 1735

Enhanced Queued Analog-to-Digital Converter (EQADC)
MPC5644A Microcontroller Reference Manual, Rev. 6
1090 Freescale Semiconductor
system memory. When a CFIFO is not full, the EQADC sets the corresponding CFFF bit in
Section 25.5.2.9, EQADC FIFO and Interrupt Status Registers (EQADC_FISR) . If CFFE is asserted in
Section 25.5.2.8, EQADC Interrupt and DMA Control Registers (EQADC_IDCR) , the EQADC generates
requests for more commands from a CQueue. An interrupt request, served by the host CPU, is generated
when CFFS is negated, and a DMA request, served by the DMAC, is generated when CFFS is asserted.
The host CPU or the DMAC respond to these requests by writing to the
Section 25.5.2.5, EQADC CFIFO
Push Registers (EQADC_CFPR) , to fill the CFIFO.
NOTE
The DMAC should be configured to write a single command (32-bit data)
to the CFIFO push registers for every asserted DMA request it
acknowledges. Refer to
Section 25.7.2, EQADC/DMAC Interface , for
DMAC configuration guidelines.
NOTE
CFIFO0 can be configured to work in an alternative way called Streaming
Mode. This mode is very different from the mode described here because it
maintains some stored commands to execute them several times in sequence
and in loop.
NOTE
Only whole words must be written to EQADC_CFPR. Writing half-words
or bytes to EQADC_CFPR will still push the whole 32-bit CF_PUSH field
into the corresponding CFIFO, but undefined data will fill the areas of
CF_PUSH that were not specifically designated as target locations for
writing.
Figure 25-60 describes the important components in the CFIFO. Each CFIFO is implemented as a circular
set of registers to avoid the need to move all entries at each push/pop operation. The Push Next Data
Pointer points to the next available CFIFO location for storing data written into the EQADC Command
FIFO Push Register. The Transfer Next Data Pointer points to the next entry to be removed from CFIFOx
when it completes a transfer. The
CFIFO Transfer Counter Control Logic counts the number of entries in
the CFIFO and generates DMA or interrupt requests to fill the CFIFO. TNXTPTR in Section 25.5.2.9,
EQADC FIFO and Interrupt Status Registers (EQADC_FISR) , indicates the index of the entry that is
currently being addressed by the Transfer Next Data Pointer, and CFCTR, in the same register, provides
the number of entries stored in the CFIFO. Using TNXTPTR and CFCTR, the absolute addresses for the
entries indicated by the Transfer Next Data Pointer and by the Push Next Data Pointer can be calculated
using the following formulas:
Transfer Next Data Pointer Address = CFIFOx_BASE_A TNXTPTRx*4
Push Next Data Pointer Address = CFIFOx_BASE_A
[(TCFCTRx) mod CFIFO_DEPTH] * 4
where
• a mod b returns the remainder of the division of a by b .
• CFIFOx_BASE_ADDRESS is the smallest memory mapped address allocated to a CFIFOx entry.