NXP Semiconductors MPC5644A, Reference Manual, Page: 318 / 1735

External Bus Interface (EBI)
MPC5644A Microcontroller Reference Manual, Rev. 6
318 Freescale Semiconductor
between the accesses unless that access is the end of a 64-bit boundary. In this case, an extra cycle is
required between TA and the next TS in order to get the next 64-bits of write data internally and RD_WR
negates during this extra cycle.
Figure 14-28. 32-Byte Write Cycle with External TA, Basic Timing
14.5.2.6.3 Small access example #3: 32-byte read to 32-bit port with BL=1
Figure 14-29 shows an example of a 32-byte read to a 32-bit burst enabled port with burst length of 4
words, requiring two 16-byte external transactions. For this case, the address for the 2nd 4-word burst
access is calculated by adding 0x10 to the lower 5 bits of the 1st address (no carry), and then masking out
the lower 4 bits to fix them at zero.
Table 14-14. Examples of 4-word Burst Addresses
1st Address
Lower 5 bits of 1st A
0x10 (no carry)
Final 2nd Address (After
Masking Lower 4 Bits)
0x000 0x10 0x10
0x008 0x18 0x10
0x010 0x00 0x00
0x018 0x08 0x00
0x020 0x30 0x30
0x028 0x38 0x30
0x030 0x20 0x20
0x038 0x28 0x20
DATA is valid DATA is valid
CLKOUT
ADDR[3:31]
TS
TA
RD_WR
BDIP
WE
CS[ n ]
A A + 4 A + 8 A + 0xc
DATA is valid
This extra cycle is required after accesses 2, 4, and 6 to get the next 64-bits of internal write data.
*
Four more external accesses (not shown) are required to complete the internal 32-byte request.
The timing of these is the same as accesses 1-4 shown in this diagram.
**
1 2 3 4** *
DATA[0:31]