NXP Semiconductors MPC5644A, Reference Manual, Page: 823 / 1735

Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 823
24.5.1.4 Watchdog
Each engine has a watchdog mechanism to prevent a thread or a sequence of threads from running too long,
impacting the latency of the other channel services. The watchdog is configured through the register
ETPU_WDTR (see
Section 24.4.4.1, ETPU_WDTR – eTPU Watchdog Timer Register ). When the
watchdog is enabled, an internal counter increments on each microcycle when a thread is executing. If the
count is greater than the value specified in the ETPU_WDTR field WDCNT and a thread is still executing,
the watchdog:
1. Forces an END of the thread
2. Issues a Global Exception and sets the ETPU_MCR bit WDTO (see Section 24.4.2.1, ETPU_MCR
– eTPU Module Configuration Register ).
The watchdog can be configured in one of the following modes, defining how the internal watchdog count
is reset:
• Thread Length Mode : the watchdog count is reset at the end of each thread.
• Busy Length Mode : the watchdog count is reset when the microengine goes idle. A sequence of
threads, one right after another, keeps the count running. The counter is also reinitialized when a
thread is forced to end, so that a new count begins if another TST initiates at the following
microcycle.
The following applies to the watchdog mechanism:
• Microcycles during TST and SDM access wait-states (on TST or instruction execution) are
counted.
• If the watchdog count equals WDCNT in the last microinstruction (with SDM wait-states or not)
of a thread servicing a channel.
• If the watchdog count expires (gets greater than WDCNT) during the TST, the thread is forced end
on its first instruction.
• The watchdog count does not wrap, so that a thread (in thread length mode) or a thread sequence
(in busy length mode) that lasts for more than the maximum value of WDCNT does get a forced
end.
NOTE
Watchdog must not be enabled when the microengine enters halt mode.
The counter does not run when the engine is stopped, and resets when the
watchdog is disabled.
24.5.2 Host interface
24.5.2.1 System configuration
System Configuration Registers are described in Section 24.4.2, System configuration registers . Detailed
explanation on the configured functionalities is found throughout Section 24.5, Functional description ,
and a specification for the initial configuration sequence is found on Section 24.6.1, Configuration
sequence .