NXP Semiconductors MPC5644A, Reference Manual, Page: 969 / 1735

Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 969
Note that MISC can run regardless of SCM implementation type (RAM or ROM).
If SCMMISEN = 0 or VIS = 1, the MISC logic stays at its initial state, with address counter pointing to the
last SCM position and accumulator reset.
24.5.10.4 Performance monitoring features
24.5.10.4.1 Idle Counter
The Idle Counter Register ETPU_IDLE (see Section 24.4.4.2, ETPU_IDLE – eTPU Idle Register )
continuously counts microcycles in which the microengine is not busy with channel service. It can be used
to measure the microengine utilization by rating the count measured during a period of time to the number
of microcycles contained in the period. The Idle counter does not count microcycles when the engine is
stopped, or is in TST or halt states.
24.6 Initialization/Application information
24.6.1 Configuration sequence
After initial power-on reset the eTPU remains in an idle state
1
, requiring initialization of several registers
before any function can begin execution. Also, if the SCM is implemented in RAM, it should be initialized
with the eTPU application code prior to configuring the eTPU. Configuration procedures are summarized
as follows:
• If SCM is implemented as RAM, load the eTPU application code (see Section 24.5.2.6, SCM
access ).
• Initialize the SCM MISC logic (optional, see Section 24.5.10.3.1, SCM Test – Multiple input
signature calculator ).
• Initialize the eTPU time base configuration registers (ETPU_TBCR) to setup:
— TCR1 and TCR2 prescalers and clock sources.
— Select digital filtering mode.
— TCRCLK signal filter control.
— Angle mode operation (if necessary).
• Initialize the eTPU engine configuration register(s) (ETPU_ECR) to setup:
— Entry table base.
— Filter prescaler clock control.
• Initialize eTPU STAC configuration register(s) (ETPU_REDCR), if one needs to setup TCR1/2
resource Client/Server operation.
• Write to the Channel Configuration registers (ETPU_CxCR) to choose the Function to be
performed by each channel, and its parameter base address.
• Write to channel status control register (ETPU_CxSCR) to choose among the possible variations
within the function flow (FM bits).
• Write to SPRAM for parameter initialization of each configured channel.
1. Except when device debug request is asserted on power-on reset: in this case, the microengines wake-up in halt state.