NXP Semiconductors MPC5644A, Reference Manual, Page: 968 / 1735

Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
968 Freescale Semiconductor
microengines can run code from both ROM and Emulation RAM. It is possible to make one engine run
code from RAM and the other from ROM, by using different Entry Tables. The SCM visibility conditions
also apply to Emulation RAM.
All SCM implementations, either RAM, ROM or Emulation RAM, are external to the eTPU block. eTPU
provides a signal to enable the switching between external SCM banks. The conditions for this switching
are:
1. Both engines stopped
2. VIS bit = 0
Note that these conditions also stop the clocks of the SCM interface and MISC logic.
24.5.10.3 Test support features
24.5.10.3.1 SCM Test – Multiple input signature calculator
The Multiple Input Signature Calculator (MISC) comprises special hardware that sequentially reads all
SCM positions and calculates, in parallel, a 32-bit signature from a 32-input CRC signature calculator with
the following polynomial:
1 + x
1
+ x
2
+ x
22
+ x
31
A complete description of the signature calculation procedure can be found in Section 24.7.4, MISC
algorithm .
Once started by the Host the MISC runs continuously, restarting after the completion of each cycle, when
it sets the ETPU_MCR flag SCMMISC (see
Section 24.4.2.1, ETPU_MCR – eTPU Module Configuration
Register ). The average time for a MISC calculation can be measured by checking SCMMISC state at
regular intervals, incrementing a counter and clearing SCMMISC if it is set.
MISC accesses to the SCM array are executed if none of the engines is accessing the SCM, to avoid
degradation of the microengine performance: it happens while no channel is being serviced. An ongoing
MISC operation can be aborted by writing 0 to SCMMISEN.
The Host must load the register ETPU_MISCCMPR (see Section 24.4.2.3, ETPU_MISCCMPR – eTPU
MISC Compare Register ) with the expected value to be found at the end of the MISC cycle, and then start
the signature calculation writing bit SCMMISEN = 1 in register ETPU_MCR (see Section 24.4.2.1,
ETPU_MCR – eTPU Module Configuration Register ). MISC zeroes the signature accumulator and starts
reading SCM data and calculating the signature. After last SCM position is read, MISC compares the value
in signature accumulator against the value in ETPU_MISCCMPR: if there is a mismatch MISC stops, a
Global Exception is issued and the bit SCMMISF in register ETPU_MCR assumes value 1. If no mismatch
is found, MISC repeats the procedure automatically. When signature is being calculated, SCM address
starts at the last SCM address and counts down to 0. The conditions for executing a MISC operation are
(see also
Table 24-38 ):
• Both microengines in idle state (no channel is being serviced) or stopped, in any combination (e.g.,
engine 1 idle with engine 2 stopped)
• ETPU_MCR bit VIS = 0
• ETPU_MCR bit SCMMISEN = 1