NXP Semiconductors MPC5644A, Reference Manual, Page: 999 / 1735

Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 999
24.7.4 MISC algorithm
The MISC generator is based on the following polynomial:
G(x) = 1 + x
1
+ x
2
+ x
22
+ x
31
(equivalent to feedback mask = 0x80400007)
The MISC signature generation starts by clearing the MISC Accumulator value to 0 and preloading the
MISC Counter with the highest SCM address. It then steps through each address decrementing the counter,
reading 32 bit values and following the algorithm below:
If the least significant bit in MISC is 1 then
MISC = MISC right shifted by 1 bit
MISC = MISC XOR 0x80400007
else
MISC = MISC right shifted by 1 bit
end if
MISC = MISC XOR RAM data
The code example below shows an excerpt of C code that calculates the MISC signature for a given array
of data, based on the previous algorithm:
#define SCM_size (MAX_SCM_ADDRESS / 4) /* last byte address - converted to 32-bit word */
#define POLY 0x80400007 /* G(x) = 1 + x
1
+ x
2
+ x
22
+ x
31
*/
/*******************************************************************************
FUNCTION : void calc_misc()
PURPOSE : This function calculates the MISC value.
INPUTS NOTES : none
RETURNS NOTES : MISC value
GENERAL NOTES : the array’unsigned int data[]’ represents the actual memory
array, organized in 32-bit words.
*******************************************************************************/
unsigned int calc_misc (void)
{
int j; /* loop counter */
unsigned int misc = 0;
for (j = (SCM_size-1); j >= 0 ; j--) { /* SCM_size has the number of 32-bit words in SCM */
if (misc & 0x1) {
misc >>= 1;
misc ^= POLY;
}
else {
misc >>= 1;
}
misc ^= data[j]; /* data[j] is the actual 32-bit word taken from the SCM array */
}
return (misc); /* final signature calculated */
};
The value calculated by this algorithm must be loaded into register ETPU_MISCCMPR prior to activating
the SCM MISC calculator in eTPU. Once the MISC calculator is activated (bit SCMMISEN in register