Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
829
24.5.2.6.2
SCM low power
SCM turns off its internal clocks when both engines are stopped (ETPU_ECR bit STF asserted), VIS = 0
at ETPU_MCR, and MISC is not enabled (SCMMISEN = 0). The SCM clocks are automatically turned
on if either one of the STF bits is negated or VIS turns to 1, or SCMMISEN turns to 1.
SCM clocks are not turned off if any of the engines is not stopped, even if they are both halted.
The conditions for SCM Clocks and MISC activation are summarized in
.
24.5.2.6.3
SCM off-range data
When read accesses are made, either by the Host or by a microengine, to addresses above the limit
corresponding to the SCMSIZE value in ETPU_MCR, the value read comes from the register
ETPU_SCMOFFDATAR. The Host can program the register at initialization with an opcode value with
operations that try to protect or recover the system from runaway code, for instance: terminate the thread,
clear channel flags, disable match and transition service requests, issue an interrupt, jump to an error
recovery procedure
1
. Writes to unimplemented addresses do not return error and can write on unspecified
mirror addresses, so they should be avoided.
24.5.3
Scheduler
Every Function is composed of one or more Threads. A Thread consists of a group of instructions that,
once begins execution, cannot be interrupted by host or channel events. Each active channel intents to be
serviced, being granted time for Thread execution. Since one microengine handles several channels
operating concurrently, the Function threads must be executed serially.
Table 24-38. SCM clocks and MISC activation
ETPU_ECR_1
STF
ETPU_ECR_2
STF
ETPU_MCR
VIS
ETPU_MCR
SCMMISEN
SCM clocks
MISC
0
x
0
1
1
VIS cannot be written 1 if ETPU_ECR_1 bit STF = 0 or ETPU_ECR_2 bit STF = 0, and both HLTF bits are 0.
1
On
On
0
x
0
On
off
x
0
1
On
On
x
0
0
On
off
1
1
0
0
off
off
1
1
0
1
On
On
1
2
2
If VIS = 1, neither MDIS can be written 0 nor the engine leave Stop Mode, regardless of device stop request.
1
0
On
off
1
1
1
On
off
3
3
MISC resets and stays so when VIS = 1, restarting automatically when VIS goes 0 if SCMMISEN = 1.
0
0
x
0
On
off
0
0
x
1
On
On
1. Only part of these suggested operations can be parallelized in a single instruction, see
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