NXP Semiconductors MPC5644A, Reference Manual, Page: 840 / 1735

Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
840 Freescale Semiconductor
The following rules specify the access priorities for contended access. They keep compatibility with the
TPU3 dual-parameter access atomicity, but only between the microengine and CDC (not Host accesses
through slave bus).
1. Microengine accesses from the two eTPU engines are interleaved between each other, but not with
Host or CDC accesses;
2. The eTPU microengine(s) gives priority for SPRAM accesses to either the Host CPU or the CDC
under any of the following conditions:
a) The microengine has completed accessing the second parameter in a back-to-back SPRAM
access
1
.
b) The SPRAM was not accessed during the last arbitration slot for the microengine and the host
does not loose the access to the other engine in the current arbitration slot
2
.
c) CDC is transferring data, after its first (read) access. Note that the CDC can be in middle of a
data transfer of another pair of parameters, unrelated to the ones that microengine tries to
access.
3. The eTPU microengine takes priority for SPRAM accesses under either of the following
conditions:
a) The Host CPU or CDC has done a data transfer during the last access arbitration slot for the
engine
2
. Also, the Host CPU does not hold a pending access against the other eTPU
microengine.
b) The microengine is arbitrating for the access of its second parameter in a back-to-back access
1
.
All pairs of back-to-back parameter accesses are coherent with respect to Host and CDC (not
to the other microengine).
The direction (read or write) of any individual access by Host or microengine is irrelevant to the
arbitration. The use of Normal or PSE SPRAM area by the Host is also irrelevant to the arbitration.
The first parameter preloading in a TST is considered first access by the arbiter, regardless of any access
made at the END microinstruction of the previous thread, i.e.: the last access of a thread and the first
preload are never considered a back-to-back access. On the other hand, the TST preload accesses are
considered back-to-back and are, therefore, atomic with respect to Host or CDC.
NOTE
The Zero SPRAM operation (see Section 24.5.9.1.5, Zero SPRAM
operation ) is considered an SPRAM access for arbitration purposes both on
writes and reads; the fact that read SPRAM data is discarded is irrelevant for
arbitration.
24.5.5 Enhanced Channels
Enhanced Channels comprise hardware support for input digital signal processing and output signal
generation. Each Channel is associated with one input and one output signal. Enhanced Channel logic is
1. If microengine tries to access the SPRAM in the following microcycles, the third and fourth consecutive accesses are
considered the first and second of a new back-to-back dual access.
2. The microengine access slot is between its own T4 and T2 edges (see
Section 24.7.1, Microcycle and I/O timing ).