NXP Semiconductors MPC5644A, Reference Manual, Page: 1334 / 1735

Deserial Serial Peripheral Interface (DSPI)
MPC5644A Microcontroller Reference Manual, Rev. 6
1334 Freescale Semiconductor
• For DSCK = 0

1/2 SCK period: For this value, the value for the DSPI is 20 ns
30.10.6 Calculation of FIFO pointer addresses
Complete visibility of the TX and RX FIFO contents is available through the FIFO registers, and valid
entries can be identified through a memory mapped pointer and a memory mapped counter for each FIFO.
The pointer to the first-in entry in each FIFO is memory mapped. For the TX FIFO the first-in pointer is
the Transmit Next Pointer (TXNXTPTR). For the RX FIFO the first-in pointer is the Pop Next Pointer
(POPNXTPTR).
Figure 30-59 illustrates the concept of first-in and last-in FIFO entries along with the
FIFO Counter. The TX FIFO is chosen for the illustration, but the concepts carry over to the RX FIFO.
See
Section 30.9.2.4, Transmit first-in first-out (TX FIFO) buffering mechanism , and Section 30.9.2.5,
Receive first-in first-out (RX FIFO) buffering mechanism , for details on the FIFO operation.
Table 30-47. DSPI Compatibility with MPC500 family QSPI
MPC500 family control bits
DSPI corresponding control bits
Corresponding DSPI_CTAR configuration
BITS
E
CTAS[0] DT CTAS[1] DSCK CTAS[2]
DSPI_CTAR
x
FMSZ PDT DT PCSSCK CSSCK
0 0 0 0 1111 10 0011 00 0000
0 0 1 1 1111 10 0011 user user
0 1 0 2 1111 user
1
1
Selected by user
user 00 0000
0 1 1 3 1111 user user user user
1 0 0 4 user 10 0011 00 0000
1 0 1 5 user 10 0011 user user
1 1 0 6 user user user 00 0000
1 1 1 7 user user user user user