NXP Semiconductors MPC5644A, Reference Manual, Page: 1335 / 1735

Deserial Serial Peripheral Interface (DSPI)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1335
Figure 30-59. TX FIFO pointers and counter
30.10.6.1 Address calculation for the first-in entry and last-in entry in the TX FIFO
The memory address of the first-in entry in the TX FIFO is computed by the following equation:
Eqn. 30-7
The memory address of the last-in entry in the TX FIFO is computed by the following equation:
Eqn. 30-8
TX FIFO Base: Base address of TX FIFO
TXCTR: TX FIFO Counter
TXNXTPTR: Transmit Next Pointer
TX FIFO Depth: Transmit FIFO depth, implementation-specific
30.10.6.2 Address calculation for the first-in entry and last-in entry in the RX FIFO
The memory address of the first-in entry in the RX FIFO is computed by the following equation:
Eqn. 30-9
The memory address of the last-in entry in the RX FIFO is computed by the following equation:
Eqn. 30-10
RX FIFO Base: Base address of RX FIFO
RXCTR: RX FIFO counter
POPNXTPTR: Pop Next Pointer
RX FIFO Depth: Receive FIFO depth, implementation specific
Push TX FIFO Register
Transmit Next
Data Pointer
Shift Register
SOUT
+1
-1
TX FIFO Counter
TX FIFO Base
—
—
Entry A (first-in)
Entry B
Entry C
Entry D (last-in)
—
—
First-in Entry Address TX FIFO Base 4 TXNXTPTR
  
+ =
Last-in Entry address TX FIFO Base 4 TXCTR TXNXTPTR 1 – +
  
mod TXFIFOdepth
 
+ =
First-in Entry Address RX FIFO Base 4 POPNXTPTR
  
+ =
Last-in Entry address RX FIFO Base 4 RXCTR POPNXTPTR 1 – +
  
mod (RXFIFOdepth) + =