NXP Semiconductors MPC5644A, Reference Manual, Page: 615 / 1735

Software Watchdog Timer (SWT)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 615
Offset 0x0000 Access: Read/Write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R MAP
0
MAP
1
MAP
2
MAP
3
MAP
4
MAP
5
MAP
6
MAP
7
0 0 0 0 0 0 0 0
W
Reset
1
1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 KEY RIA WND ITR HLK SLK CSL STP FRZ WEN
W
Reset 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0
Figure 20-1. SWT Module Control Register (SWT_MCR)
Table 20-2. SWT_MCR field description
Field Description
MAPn Master Access Protection for Master n
The platform bus master assignments are device specific.
0 = Access for the master is not enabled
1 = Access for the master is enabled
KEY Keyed Service Mode
0 = Fixed Service Sequence, the fixed sequence 0xA602, 0xB480 is used to service the watchdog
1 = Keyed Service Mode, two pseudorandom key values are used to service the watchdog
RIA Reset on Invalid Access
0 = Invalid access to the SWT generates a bus error
1 = Invalid access to the SWT causes a system reset if WEN = 1
WND Window Mode
0 = Regular mode, service sequence can be done at any time
1 = Windowed mode, the service sequence is only valid when the down counter is less than the value
in the SWT_WN register.
ITR Interrupt Then Reset
0 = Generate a reset on a time-out
1 = Generate an interrupt on an initial time-out, reset on a second consecutive time-out
HLK Hard Lock
This bit is only cleared at reset.
0 = SWT_MCR, SWT_TO, SWT_WN and SWT_SK are read/write registers if SLK = 0
1 = SWT_MCR, SWT_TO, SWT_WN and SWT_SK are read-only registers
SLK Soft Lock
This bit is cleared by writing the unlock sequence to the service register.
0 = SWT_MCR, SWT_TO SWT_WN and SWT_SK are read/write registers if HLK = 0
1 = SWT_MCR, SWT_TO, SWT_WN and SWT_SK are read-only registers
CSL Clock Selection
Selects the clock that drives the internal timer
0 = System clock
1 = Oscillator clock