NXP Semiconductors MPC5644A, Reference Manual, Page: 573 / 1735

Frequency-modulated phase locked loop (FMPLL)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 573
Offset 0x0018 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R BSY MOD
EN
MOD
SEL
MODPERIOD
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0
INCSTEP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 17-6. Synthesizer FM Modulation Register (SYNFMMR)
Table 17-10. SYNFMMR field descriptions
Field Description
0
BSY
Busy
This bit is asserted soon after a write access to the FMPLL_SYNFMMR, and remains asserted while
the FMPLL processes the new frequency modulation programming. The CPU must wait until this bit
is negated before attempting another write access to this register. Any write attempt while the BSY
flag is set will have no effect.
0 Write to the FMPLL_SYNFMMR is allowed.
1 The FMPLL is still busy processing the previous change on the FMPLL_SYNFMMR; write access
to the register is not possible.
1
MODEN
Modulation enable
This bit enables the frequency modulation.
0 Frequency modulation disabled
1 Frequency modulation enabled
2
MODSEL
Modulation selection
This bit selects whether modulation will be centered around the nominal frequency or spread below
the nominal frequency.
0 Modulation centered around nominal frequency.
1 Modulation spread below nominal frequency.
3–15
MODPERIOD
Modulation period
This 13-bit field is the binary equivalent of the modperiod variable derived from the formula:
where f
fbk
represents the frequency of the feedback divider, and f
mod
represents the modulation
frequency.
modperiod round
f
fbk
4 f
mod

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