Interrupt Controller (INTC)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
353
Although INTC_SSCI
n
is 8 bits wide, it can be accessed with a single 16-bit or 32-bit access, provided
that the access does not cross a 32-bit boundary.
Figure 15-12. INTC Software Set/Clear Interrupt Register (INTC_SSCIRn)
15.4.1.6
INTC Priority Select Registers (INTC_PSR0–485)
The INTC_PSR
n
allows you to select a priority for each interrupt request source (peripheral IRQs or
software configurable IRQs). Each priority select register (INTC_PSR
n)
is assigned to the IRQ source
vector with the same number. For example, the software configurable IRQs 0–7 are assigned vectors 0–7,
and their priorities are configured in INTC_PSR0–INTC_PSR7, respectively. The peripheral interrupt
requests are assigned vectors 8–485 and their priorities are configured in priority select registers
INTC_PSR8 through INTC_PSR485, respectively.
Although INTC_PSR
n
is 8-bits wide, you can use a single 16-bit or 32-bit access, provided that it does not
cross a 32-bit boundary.
NOTE
Do not modify the PRI
n
field in INTC_PSR
n
when the IRQ is asserted.
Address: Base +
n
(INTC_SSCIR
n
);
n
= 0–7
Access: R/W
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
0
0
0
0
0
0
0
CLR0
0
0
0
0
0
0
0
CLR1
W
SET0
SET1
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
0
0
0
0
0
0
0
CLR2
0
0
0
0
0
0
0
CLR3
W
SET2
SET3
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Table 15-6. INTC_SSCIRn Field Descriptions
Field
Description
0–5
Reserved, must be cleared.
6
SET
n
Set flag bits. Writing a 1 sets the corresponding CLR
n
bit. Writing a 0 has no effect. Each SET
n
is always
read as a 0.
7
CLR
n
Clear flag bits. CLR
n
is the flag bit. Writing a 1 to CLR
n
clears it provided that a 1 is not written
simultaneously to its corresponding SET
n
bit. Writing a 0 to CLR
n
has no effect.
0 Interrupt request not pending within INTC.
1 Interrupt request pending within INTC.
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