NXP Semiconductors MPC5644A, Reference Manual, Page: 349 / 1735

Interrupt Controller (INTC)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 349
15.4.1.1 INTC Module Configuration Register (INTC_MCR)
The INTC_MCR is used to configure options of the INTC.
Figure 15-7. INTC Module Configuration Register (INTC_MCR)
15.4.1.2 INTC Current Priority Register (INTC_CPR)
The INTC_CPR masks any peripheral or software configurable interrupt request set at the same or lower
priority as the current value of the INTC_CPR[PRI] field from generating an interrupt request to the
processor. When the INTC interrupt acknowledge register (INTC_IACKR) is read in the software vector
mode or the interrupt acknowledge signal from the processor is asserted in the hardware vector mode, the
value of PRI is pushed onto the LIFO, and PRI is updated with the priority of the preempting interrupt
request. When the INTC end-of-interrupt register (INTC_EOIR) is written, the LIFO is popped into the
INTC_CPR’s PRI field.
The masking priority can be raised or lowered by writing to the PRI field, supporting the PCP. Refer to
Section 15.6.5, Priority ceiling protocol .
Address: Base + 0x0000 (INTC_MCR Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0
VTES
0 0 0 0
HVEN
W
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Table 15-3. INTC_MCR Field Descriptions
Field Description
0–25 Reserved, must be cleared.
26
VTES
Vector table entry size. Controls the number of ‘0’s to the right of INTVEC in Section 15.4.1.3, INTC
Interrupt Acknowledge Register (INTC_IACKR) . If the contents of INTC_IACKR are used as an address
of an entry in a vector table as in software vector mode, then the number of rightmost ‘0’s determines the
size of each vector table entry.
VTES impacts software vector mode operation but also affects the INTC_IACKR[INTVEC] position in both
hardware vector mode and software vector mode.
0 4 bytes (Normal expected use)
1 8 bytes
27–30 Reserved, must be cleared.
31
HVEN
Hardware vector enable. Controls whether the INTC is in hardware vector mode or software vector mode.
Refer to
Section 15.2.4, Modes of operation ”, for the details of the handshaking with the processor in each
mode.
0 Software vector mode
1 Hardware vector mode