NXP Semiconductors MPC5644A, Reference Manual, Page: 1466 / 1735

FlexRay Communication Controller (FlexRay)
MPC5644A Microcontroller Reference Manual, Rev. 6
1466 Freescale Semiconductor
support . These flags are cleared automatically when all of the corresponding interrupt flags or interrupt
enables in the related interrupt flag and enable registers are cleared by the application.
Table 33-17. FR_GIFER field description
Field Description
MIF Module Interrupt Flag — This flag is asserted if at least one of the other interrupt flags in this register
and its related interrupt enable is asserted.
0 No interrupt flag is asserted or no interrupt enable is set
1 At least one of the other interrupt flags in this register is asserted and the related interrupt bit is
asserted, too
PRIF Protocol Interrupt Flag — This flag is set if at least one of the individual protocol interrupt flags in the
Protocol Interrupt Flag Register 0 (FR_PIFR0) and Protocol Interrupt Flag Register 1 (FR_PIFR1) is
asserted and the related interrupt enable flag is asserted.
0 All individual protocol interrupt flags are equal to 0 or no interrupt enable bit is set.
1 At least one of the individual protocol interrupt flags and the related interrupt enable is equal to 1.
CHIF CHI Interrupt Flag — This flag is set if at least one of the individual CHI error flags in the CHI Error
Flag Register (FR_CHIERFR) is asserted and the CHI error interrupt enable FR_GIFER[CHIE] is
asserted.
0 All CHI error flags are equal to 0 or the CHI error interrupt is disabled
1 At least one CHI error flag is asserted and CHI error interrupt is enabled
WUPIF Wakeup Interrupt Flag — This flag is set when the CC has received a wakeup symbol on the FlexRay
bus. The application can determine on which channel the wakeup symbol was received by reading the
related wakeup flags WUB and WUA in the
Protocol Status Register 3 (FR_PSR3).
0 No wakeup condition or interrupt disabled
1 Wakeup symbol received on FlexRay bus and interrupt enabled
FAFBIF Receive FIFO Channel B Almost Full Interrupt Flag — This flag is set when one of the following
events occurs
a) the current number of FIFO B entries is equal to or greater than the watermark defined by the WM
field in the
Receive FIFO Watermark and Selection Register (FR_RFWMSR) , and the CC writes a
received message into the FIFO B, or
b) the current number of FIFO B entries is at least 1 and the periodic timer as defined by
Receive FIFO
Periodic Timer Register (FR_RFPTR) expires.
0 no such event
1 FIFO B almost full event has occurred
FAFAIF Receive FIFO Channel A Almost Full Interrupt Flag — This flag is set when one of the following
events occurs
a) the current number of FIFO A entries is equal to or greater than the watermark defined by the WM
field in the
Receive FIFO Watermark and Selection Register (FR_RFWMSR) , and the CC writes a
received message into the FIFO A, or
b) the current number of FIFO B entries is at least 1 and the periodic timer as defined by
Receive FIFO
Periodic Timer Register (FR_RFPTR) expires.
0 no such event
1 FIFO A almost full event has occurred
RBIF Receive Message Buffer Interrupt Flag — This flag is set if for at least one of the individual receive
message buffers (FR_MBCCSRn[MTD] = 0) both the interrupt flag MBIF and the interrupt enable bit
MBIE in the corresponding
Message Buffer Configuration, Control, Status Registers (FR_MBCCSRn)
are asserted. The application can not clear this RBIF flag directly. This flag is cleared by the CC when
all of the interrupt flags MBIF of the individual receive message buffers are cleared by the application
or if the application has cleared the interrupt enables bit MBIE.
0 None of the individual receive message buffers has the MBIF and MBIE flag asserted.
1 At least one individual receive message buffer has the MBIF and MBIE flag asserted.