FlexRay Communication Controller (FlexRay)
MPC5644A Microcontroller Reference Manual, Rev. 6
1482
Freescale Semiconductor
33.5.2.24 Protocol Status Register 3 (FR_PSR3)
This register provides aggregated channel status information as an accrued status of channel activity for
all communication slots, regardless of whether they are assigned for transmission or subscribed for
reception. It provides accrued information for the symbol window, the NIT, and the wakeup status.
STCA
Symbol Window Transmit Conflict on Channel A
— protocol related variable:
vSS!TxConflict
for
symbol window on channel A
This status bit is set if there was a transmission conflicts during the symbol window on channel A.
0 No such event
1 Transmission conflict detected
SBVA
Symbol Window Boundary Violation on Channel A
— protocol related variable:
vSS!BViolation
for
symbol window on channel A
This status bit is set if there was some media activity on the FlexRay bus channel A at the start or at
the end of the symbol window.
0 No such event
1 Media activity at boundaries detected
SSEA
Symbol Window Syntax Error on Channel A
— protocol related variable:
vSS!SyntaxError
for
symbol window on channel A
This status bit is set when a syntax error was detected during the symbol window on channel A.
0 No such event
1 Syntax error detected
MTA
Media Access Test Symbol MTS Received on Channel A
— protocol related variable:
vSS!ValidMTS
for symbol window on channel A
This status bit is set if the Media Access Test Symbol MTS was received in the symbol window on
channel A.
1 MTS symbol received
0 No such event
CLKCORR-
FAILCNT
Clock Correction Failed Counter
— protocol related variable:
vClockCorrectionFailed
This field provides the number of consecutive even/odd communication cycle pairs that have passed
without clock synchronization having performed an offset or a rate correction due to lack of
synchronization frames. It is not incremented when it has reached the configured value of either
max_without_clock_correction_fatal or max_without_clock_correction_passive as defined in the
Protocol Configuration Register 8 (FR_PCR8)
. The CC resets this counter on a hard reset condition,
when the protocol enters the
POC:normal active
state, or when both the rate and offset correction
terms have been calculated successfully.
Base + 0x002E
Additional Reset: RUN Command
Write: Normal Mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
0
0
WUB
ABV
B
AA
CB
ACEB
ASE
B
AV
F
B
0
0
WUA
ABV
A
AA
CA
ACEA
ASE
A
AV
F
A
W
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 33-24. Protocol Status Register 3 (FR_PSR3)
Table 33-28. FR_PSR2 field description (continued)
Field
Description
Summary of Contents for MPC5644A
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