NXP Semiconductors MPC5644A, Reference Manual, Page: 799 / 1735

Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 799
24.4.6.7 ETPU_CPSSR – eTPU Channel Pending Service Status Register
ETPU_CPSSR is a read-only register that holds the status of the pending Channel Service Requests (see
Section 24.5.1, Functions and threads ).
Figure 24-19. ETPU_CPSSR Register
24.4.6.8 ETPU_CSSR – eTPU Channel Service Status Register
ETPU_CSSR holds the current channel service status on whether it is being serviced or not (see
Section 24.5.1, Functions and threads ). Only one bit may be asserted in this register at a given time. When
no channel is being serviced the register read value is 0x00000000. ETPU_CSSR is a read-only register.
The register can be read during normal eTPU operation for monitoring the scheduler activity.
Offset: eTPU_A: eTP 0x280; eTPU_B: eTP 0x284 Access: User read
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R SR31 SR30 SR29 SR2
8
SR2
7
SR2
6
SR2
5
SR2
4
SR23 SR22 SR2
1
SR2
0
SR1
9
SR1
8
SR1
7
SR1
6
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R SR15 SR14 SR13 SR1
2
SR11 SR1
0
SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Table 24-29. ETPU_CPSSR field description
Field Description
0-31 SRx—Pending Service Request x
Indicates a pending Service Request for channel x.
1: pending Service Request for channel x
0: no Service Request pending for channel x
Pending SR status is a logic OR of all service requests pending: if only HSR is active, SRx clears only at
the end of the thread. SRx clear due to the other request sources is microcode dependent.
Note:
The pending service status bit for a channel is 1 when a Service Request is pending, even if the Channel
is disabled (CPRx = 0).
There can be a delay of one clock between writing HSR > 0 in register ETPU_CxHSRR of a channel and
its respective bit being asserted in ETPU_CPSSR.