NXP Semiconductors MPC5644A, Reference Manual, Page: 132 / 1735

e200z4 Core
MPC5644A Microcontroller Reference Manual, Rev. 6
132 Freescale Semiconductor
• Precise exception handling
• Branch processing unit
— Dedicated branch address calculation adder
— Branch target prefetching using 8-entry BTB
• Supports independent instruction and data accesses to different memory subsystems, such as
SRAM and Flash memory via independent Instruction and Data BIUs
• Load/store unit
— 2 cycle load latency
— Fully pipelined
— Big and Little endian support
— Misaligned access support
• 64-bit General Purpose Register file
• 64-bit Instruction bus, 64-bit Data bus
• Memory Management Unit (MMU) with 24-entry fully-associative TLB and multiple page size
support
• 8 KB, 2-way or 4-way Set Associative Instruction Cache
• Signal Processing Extension (SPE1.1) APU supporting SIMD fixed-point operations using the
64-bit General Purpose Register file.
• Embedded Floating-Point (EFP2) APU supporting scalar and vector SIMD single-precision
floating-point operations, using the 64-bit General Purpose Register file.
• Nexus Class 3 real-time Development Unit
• Power management
— Power saving mode: WAIT
• Process ID manipulation for the MMU using an external tool
7.3 Microarchitecture summary
The e200z4 utilizes a five-stage pipeline for instruction execution.
These stages are:
• Instruction Fetch (stage 1)
• Instruction Decode/Register file Read/Effective Address Calculation (stage 2)
• Execute 0/Memory Access 0 (stage 3)
• Execute 1/Memory Access 1 (stage 4)
• Register Writeback (stage 5)
The stages operate in an overlapped fashion, allowing single clock instruction execution for most
instructions.
The integer execution unit consists of a 32-bit Arithmetic Unit (AU), a Logic Unit (LU), a 32-bit Barrel
shifter (Shifter), a Mask-Insertion Unit (MIU), a Condition Register manipulation Unit (CRU), a