NXP Semiconductors MPC5644A, Reference Manual, Page: 1455 / 1735

FlexRay Communication Controller (FlexRay)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1455
33.5.2.1 Register reset
All registers except the Message Buffer Cycle Counter Filter Registers (FR_MBCCFRn) , Message Buffer
Frame ID Registers (FR_MBFIDRn) , and Message Buffer Index Registers (FR_MBIDXRn) are reset to
their reset value on system reset. The registers mentioned above are located in physical memory blocks
and, thus, they are not affected by reset. For some register fields, additional reset conditions exist. These
additional reset conditions are mentioned in the detailed description of the register. The additional reset
conditions are explained in
Table 33-5 .
33.5.2.2 Register write access
This section describes the write access restriction terms that apply to all registers.
33.5.2.2.1 Register write access restriction
For each register bit and register field, the write access conditions are specified in the detailed register
description. A description of the write access conditions is given in
Table 33-6 . If, for a specific register
bit or field, none of the given write access conditions is fulfilled, any write attempt to this register bit or
field is ignored without any notification. The values of the bits or fields are not changed. The condition
term [A or B] indicates that the register or field can be written to if at least one of the conditions is
fulfilled.The condition term [A and B] indicates that the register or field can be written to if both conditions
are fulfilled.
1 Resets to one
— Not defined after reset and not affected by reset
Table 33-5. Additional register reset conditions
Condition Description
Protocol RUN Command The register field is reset when the application writes to RUN command “0101”
to the POCCMD field in the
Protocol Operation Control Register (FR_POCR) .
Message Buffer Disable The register field is reset when the application has disabled the message buffer.
This happens when the application writes 1 to the message buffer disable trigger
bit FR_MBCCSRn[EDT] while the message buffer is enabled
(FR_MBCCSRn[EDS] = 1) and the CC grants the disable to the application by
clearing the FR_MBCCSRn[EDS] bit.
Table 33-6. Register write access restrictions
Condition Indication Description
Any Time — No write access restriction
Disabled Mode FR_MCR[MEN] = 0 Write access only when CC is in Disabled Mode
Normal Mode FR_MCR[MEN] = 1 Write access only when CC is in Normal Mode
Table 33-4. Register access conventions (continued)
Convention Description