NXP Semiconductors MPC5644A, Reference Manual, Page: 369 / 1735

Interrupt Controller (INTC)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 369
peripheral or software configurable interrupt request is higher than the current priority, then the interrupt
request to the processor is asserted. Also, a unique vector for the preempting peripheral or software
configurable interrupt request is generated for INTC interrupt acknowledge register (INTC_IACKR), and
if in hardware vector mode, for the interrupt vector provided to the processor.
15.5.2.1.1 Priority arbitrator submodule
The priority arbitrator submodule compares all the priorities of all of the asserted interrupt requests, both
peripheral and software configurable. The output of the priority arbitrator submodule is the highest of
those priorities. Also, any interrupt requests which have this highest priority are output as asserted
interrupt requests to the request selector submodule.
15.5.2.1.2 Request selector submodule
If only one interrupt request from the priority arbitrator submodule is asserted, then it is passed as asserted
to the vector encoder submodule. If multiple interrupt requests from the priority arbitrator submodule are
asserted, then only the one with the lowest vector is passed as asserted to the vector encoder submodule.
The lower vector is chosen regardless of the time order of the assertions of the peripheral or software
configurable interrupt requests.
15.5.2.1.3 Vector encoder submodule
The vector encoder submodule generates the unique 9-bit vector for the asserted interrupt request from the
request selector submodule.
15.5.2.1.4 Priority comparator submodule
The priority comparator submodule compares the highest priority output from the priority arbitrator
submodule with PRI in INTC_CPR. If the priority comparator submodule detects that this highest priority
is higher than the current priority, then it asserts the interrupt request to the processor. This interrupt request
to the processor asserts whether this highest priority is raised above the value of PRI in INTC_CPR or the
PRI value in INTC_CPR is lowered below this highest priority. This highest priority then becomes the new
priority which is written to PRI in INTC_CPR when the interrupt request to the processor is
acknowledged. Interrupt requests whose PRI
n in INTC_PSR n are zero does not cause a preemption
because their PRI n is not higher than PRI in INTC_CPR.
15.5.2.2 LIFO
The LIFO stores the preempted PRI values from the INTC_CPR. Therefore, because these priorities are
stacked within the INTC, if interrupts need to be enabled during the ISR, at the beginning of the interrupt
exception handler the PRI value in the INTC_CPR does not need to be loaded from the INTC_CPR and
stored onto the context stack. Likewise at the end of the interrupt exception handler, the priority does not
need to be loaded from the context stack and stored into the INTC_CPR.
The PRI value in the INTC_CPR is pushed onto the LIFO when the INTC_IACKR is read in software
vector mode or the interrupt acknowledge signal from the processor is asserted in hardware vector mode.
The priority is popped into PRI in the INTC_CPR whenever the INTC_EOIR is written.