NXP Semiconductors MPC5644A, Reference Manual, Page: 35 / 1735

Introduction
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 35
memory containing the transfer control descriptors (TCD) for the channels. This implementation is utilized
to minimize the overall block size. The eDMA module provides the following features:
• All data movement via dual-address transfers: read from source, write to destination
• Programmable source and destination addresses, transfer size, plus support for enhanced
addressing modes
• Transfer control descriptor organized to support two-deep, nested transfer operations
• An inner data transfer loop defined by a “minor” byte transfer count
• An outer data transfer loop defined by a “major” iteration count
• Channel activation via one of three methods:
— Explicit software initiation
— Initiation via a channel-to-channel linking mechanism for continuous transfers
— Peripheral-paced hardware requests (one per channel)
• Support for fixed-priority and round-robin channel arbitration
• Channel completion reported via optional interrupt requests
• One interrupt per channel, optionally asserted at completion of major iteration count
• Error termination interrupts optionally enabled
• Support for scatter/gather DMA processing
• Ability to suspend channel transfers by a higher priority channel
1.4.5 Interrupt controller
The INTC (interrupt controller) provides priority-based preemptive scheduling of interrupt requests,
suitable for statically scheduled hard real-time systems.
For high priority interrupt requests, the time from the assertion of the interrupt request from the peripheral
to when the processor is executing the interrupt service routine (ISR) has been minimized. The INTC
provides a unique vector for each interrupt request source for quick determination of which ISR needs to
be executed. It also provides an ample number of priorities so that lower priority ISRs do not delay the
execution of higher priority ISRs. To allow the appropriate priorities for each source of interrupt request,
the priority of each interrupt request is software configurable.
When multiple tasks share a resource, coherent accesses to that resource need to be supported. The INTC
supports the priority ceiling protocol for coherent accesses. By providing a modifiable priority mask, the
priority can be raised temporarily so that all tasks which share the resource cannot preempt each other.
The INTC provides the following features:
• 9-bit vector addresses
• Unique vector for each interrupt request source
• Hardware connection to processor or read from register
• Each interrupt source can assigned a specific priority by software
• Preemptive prioritized interrupt requests to processor
• ISR at a higher priority preempts executing ISRs or tasks at lower priorities